Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 226

• Manufacturer Part Number: Z16F2811AL20SG
• Description: IC ZNEO MCU FLASH 128K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4533

PS022008-0810
When a Master loses arbitration, software is informed by means of the Arbitration Lost
interrupt. Software repeats the same transaction again at a later time.
A special case occurs when a slave transaction starts just before software attempts to start
a new master transaction by setting the
slave states before the START bit is set and the I
address match occurs and the I
cleared and an Arbitration Lost interrupt is asserted. Software minimizes the chance of this
occurring by checking the BUSY bit in the I2CSTATE register before initiating a master
transaction. If a slave address match does not occur, the Arbitration Lost interrupt does not
occur and the
once the I
Master Address Only Transactions
It is sometimes appropriate to perform an address-only transaction to determine if a
particular Slave device is able to respond. This transaction is performed by monitoring the
ACKV bit in the I2CSTATE register after the address has been written to the I2CDATA
register and the START bit has been set. Once ACKV is set, the ACK bit in the I2CSTATE
register determines if the Slave is able to communicate. The STOP bit must be set in the
I2CCTL register to terminate the transaction without transferring data. For a 10-bit slave
address, if the first address byte is acknowledged, the second address byte must also be
sent to determine if the appropriate slave is responding.
Another approach is to set both the STOP and START bits (for sending a 7-bit address).
Once both bits are cleared (7-bit address has been sent and transaction is complete), the
ACK
bit after the second TDRE interrupt (second address byte is being sent).
Master Transaction Diagrams
In the following transaction diagrams, shaded regions indicate data transferred from the
Master to the Slave and unshaded regions indicate data transferred from the Slave to the
Master. The transaction field labels are defined as follows:
•
•
•
•
•
Master Write Transaction with a 7-Bit Address
Figure 43
Slave.
S — Start
W — Write
A — Acknowledge
A — Not Acknowledge
P — Stop
bit is read to determine if the slave is acknowledged. For a 10-bit slave, set the STOP
2
on page 211 displays the data transfer format from a Master to a 7-bit addressed
C bus is no longer busy.
START
bit is not cleared. The I
P R E L I M I N A R Y
2
C Controller receives or transmits data, the
START
2
C Controller initiates the master transaction
bit. In this case the state machine enters the
2
C Controller does not arbitrate. If a slave
I
2
C Master/Slave Controller
Product Specification
ZNEO
START
Z16F Series
bit is
210