Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 104

• Manufacturer Part Number: Z16F2811AL20SG
• Description: IC ZNEO MCU FLASH 128K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4533

Table 46. Interrupt Request 2 Register (IRQ2) and Interrupt Request 2 Set Register
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
FIELD
RESET
R/W
ADDR
Note: IRQ2SET at address FF_E039H is write only and used to set the interrupts identified.
Note:
Interrupt Request 2 Register
(IRQ2SET)
PWMTI
PWMTI
R/W1C
W
These bits are set any time the selected port is toggled. The setting of these bits are not
affected by the associated interrupt enable bits.
7
0
0
Here x indicates the specific GPIO port pin number (0 through 7). PAD7I and PAD0I have
interrupt sources other than Port A and Port D as selected by the Port A Irq Mux registers.
PAD7I is configured to provide the comparator interrupt. PAD0I is configured to provide
the OCD interrupt.
The interrupt request 2 (IRQ2) register (see
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ2 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the ZNEO
CPU. If interrupts are globally disabled (polled interrupts), the ZNEO CPU reads the
interrupt request 1 register to determine, if any interrupt requests are pending. Writing 1 to
the bits in this register clears the interrupt. The bits of this register are set by writing 1 to
the interrupt request 2 set regsiter (IRQ2SET) at address FF_E039H.
PWMTI—PWM Timer Interrupt Request
0 = No interrupt request is pending for the PWM timer.
1 = An interrupt request from the PWM timer is awaiting service. Writing 1 to this bit
Resets it to 0.
R/W1C
U1RXI
U1RXI
W
6
0
0
R/W1C
U1TXI
U1TXI
W
5
0
0
P R E L I M I N A R Y
PWMFI
PWMFI
R/W1C
W
4
0
0
FF_E038H
FF_E039H
Table
R/W1C
DMA3I
DMA3I
PC3I/
PC3I/
W
3
0
0
46) stores interrupt requests for both
R/W1C
DMA2I
DMA2I
PC2I/
PC2I/
W
2
0
0
Product Specification
ZNEO
R/W1C
DMA1I
DMA1I
PC1I/
PC1I/
Interrupt Controller
W
1
0
0
Z16F Series
R/W1C
DMA0I
DMA0I
PC0I/
PC0I/
W
0
0
0
89