PIC18F96J65-I/PT Microchip Technology, PIC18F96J65-I/PT Datasheet - Page 472

• Manufacturer Part Number: PIC18F96J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
Program Counter ................................................................ 75
Program Memory
Program Memory Modes .................................................... 73
Program Verification and Code Protection ....................... 362
Programming, Device Instructions ................................... 363
PSP. See Parallel Slave Port.
Pulse-Width Modulation. See PWM (CCP Module) and PWM
PUSH ............................................................................... 392
PUSH and POP Instructions .............................................. 76
PUSHL ............................................................................. 408
PWM (CCP Module)
PWM (ECCP Module) ...................................................... 197
Q
Q Clock .................................................................... 191, 198
R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 55
RC_RUN Mode .................................................................. 52
RCALL .............................................................................. 393
RCON Register
Reader Response ............................................................ 478
DS39762E-page 472
PCL, PCH and PCU Registers ................................... 75
PCLATH and PCLATU Registers .............................. 75
Extended Instruction Set ............................................ 94
Instructions ................................................................. 79
Interrupt Vector .......................................................... 72
Look-up Tables .......................................................... 77
Memory Maps ............................................................ 71
Memory Maps, Modes ............................................... 74
Modes
Reset Vector .............................................................. 72
Address Shifting (Extended Microcontroller) .............. 74
Extended Microcontroller ........................................... 73
Microcontroller ........................................................... 73
(ECCP Module).
Associated Registers ............................................... 192
Duty Cycle ................................................................ 190
Example Frequencies/Resolutions .......................... 191
Operation Setup ....................................................... 191
Period ....................................................................... 190
TMR2 to PR2 Match ................................................ 197
TMR4 to PR4 Match ................................................ 183
CCPR1H:CCPR1L Registers ................................... 197
Direction Change in Full-Bridge Output Mode ......... 202
Duty Cycle ................................................................ 198
Effects of a Reset ..................................................... 207
Enhanced PWM Auto-Shutdown ............................. 204
Example Frequencies/Resolutions .......................... 198
Full-Bridge Application Example .............................. 202
Full-Bridge Mode ...................................................... 201
Half-Bridge Mode ..................................................... 200
Half-Bridge Output Mode Applications Example ...... 200
Output Configurations .............................................. 198
Output Relationships (Active-High) .......................... 199
Output Relationships (Active-Low) ........................... 199
Period ....................................................................... 197
Programmable Dead-Band Delay ............................ 204
Setup for PWM Operation ........................................ 207
Start-up Considerations ........................................... 205
Bit Status During Initialization .................................... 62
Two-Word .......................................................... 79
Hard Vectors and Configuration Words ............. 72
Memory Access (table) ...................................... 74
Receive Filters
Register File Summary ................................................ 85–90
Registers
AND Logic Flow ....................................................... 252
Magic Packet Format ............................................... 254
OR Logic Flow ......................................................... 251
Pattern Match Filter Format ..................................... 253
ADCON0 (A/D Control 0) ......................................... 329
ADCON1 (A/D Control 1) ......................................... 330
ADCON2 (A/D Control 2) ......................................... 331
BAUDCONx (Baud Rate Control x) ......................... 308
CCPxCON (Capture/Compare/PWM Control, CCP4 and
CCPxCON (Enhanced Capture/Compare/PWM Control,
CMCON (Comparator Control) ................................ 339
CONFIG1H (Configuration 1 High) .......................... 351
CONFIG1L (Configuration 1 Low) ........................... 351
CONFIG2H (Configuration 2 High) .......................... 353
CONFIG2L (Configuration 2 Low) ........................... 352
CONFIG3H (Configuration 3 High) .......................... 355
CONFIG3L (Configuration 3 Low) ..................... 73, 354
CVRCON (Comparator Voltage Reference Control) 345
DEVID1 (Device ID 1) .............................................. 356
DEVID2 (Device ID 2) .............................................. 356
ECCPxAS (ECCPx Auto-Shutdown Configuration) . 205
ECCPxDEL (ECCPx Dead-Band Delay) ................. 204
ECON1 (Ethernet Control 1) .................................... 217
ECON2 (Ethernet Control 2) .................................... 218
EECON1 (EEPROM Control 1) ............................... 101
EFLOCON (Ethernet Flow Control) ......................... 248
EIE (Ethernet Interrupt Enable) ............................... 230
EIR (Ethernet Interrupt Request, Flag) .................... 231
ERXFCON (Ethernet Receive Filter Control) ........... 250
ESTAT (Ethernet Status) ......................................... 218
INTCON (Interrupt Control) ...................................... 125
INTCON2 (Interrupt Control 2) ................................. 126
INTCON3 (Interrupt Control 3) ................................. 127
IPR1 (Peripheral Interrupt Priority 1) ....................... 134
IPR2 (Peripheral Interrupt Priority 2) ....................... 135
IPR3 (Peripheral Interrupt Priority 3) ....................... 136
MABBIPG (MAC Back-to-Back Inter-Packet Gap) .. 236
MACON1 (MAC Control 1) ...................................... 219
MACON3 (MAC Control 3) ...................................... 220
MACON4 (MAC Control 4) ...................................... 221
MEMCON (External Memory Bus Control) .............. 110
MICMD (MII Command) ........................................... 221
MISTAT (MII Status) ................................................ 222
OSCCON (Oscillator Control) .................................... 47
OSCTUNE (PLL Block Control) ................................. 45
PHCON1 (PHY Control 1) ....................................... 225
PHCON2 (PHY Control 2) ....................................... 226
PHIE (PHY Interrupt Enable) ................................... 232
PHIR (PHY Interrupt Request, Flag) ........................ 232
PHLCON (PHY Module LED Control) ...................... 228
PHSTAT1 (Physical Layer Status 1) ........................ 225
PHSTAT2 (Physical Layer Status 2) ........................ 227
PIE1 (Peripheral Interrupt Enable 1) ........................ 131
PIE2 (Peripheral Interrupt Enable 2) ........................ 132
PIE3 (Peripheral Interrupt Enable 3) ........................ 133
PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 128
PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 129
PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 130
CCP5) .............................................................. 185
ECCP1/ECCP2/ECCP3) ................................. 193
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