PIC18F96J65-I/PT Microchip Technology, PIC18F96J65-I/PT Datasheet - Page 248

• Manufacturer Part Number: PIC18F96J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
To enable flow control in Full-Duplex mode, set the
TXPAUS and RXPAUS bits in the MACON1 register.
Then, at any time that the receiver buffer is running out
of space, set the Flow Control Enable bits,
FCEN1:FCEN0 (EFLOCON<1:0>). The module will
automatically finish transmitting anything that was in
progress and then send a valid pause frame loaded
with the selected pause timer value. Depending on the
mode selected, the application may need to eventually
clear Flow Control mode by again writing to the FCEN
bits.
REGISTER 18-19: EFLOCON: ETHERNET FLOW CONTROL REGISTER
TABLE 18-8:
DS39762E-page 248
ECON1
MACON1
MABBIPG
EFLOCON
EPAUSL
EPAUSH
Legend: — = unimplemented, r = reserved bit. Shaded cells are not used.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-3
bit 2
bit 1-0
Register
Name
U-0
—
Pause Timer Value Register Low Byte (EPAUS<7:0>)
Pause Timer Value Register High Byte (EPAUS<15:8>)
TXRST
Unimplemented: Read as ‘0’
Reserved: Do not use
FCEN1:FCEN0: Flow Control Enable bits
When FULDPX (MACON3<0>) = 1:
11 = Send one pause frame with a ‘0’ timer value and then turn flow control off
10 = Send pause frames periodically
01 = Send one pause frame then turn flow control off
00 = Flow control off
When FULDPX (MACON3<0>) = 0:
x1 = Flow control on
x0 = Flow control off
Bit 7
—
—
—
SUMMARY OF REGISTERS USED WITH FLOW CONTROL
U-0
—
BBIPG6
RXRST
Bit 6
—
—
W = Writable bit
‘1’ = Bit is set
U-0
—
BBIPG5
DMAST
Bit 5
—
—
CSUMEN
BBIPG4
U-0
Bit 4
—
—
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXPAUS
BBIPG3
TXRTS
Bit 3
—
When the RXPAUS bit is set and a valid pause frame
arrives with a non-zero pause timer value, the module
will automatically inhibit transmissions. If the TXRTS bit
becomes set to send a packet, the hardware will simply
wait until the pause timer expires before attempting to
send the packet and subsequently, clearing the TXRTS
bit. Normally, this is transparent to the microcontroller,
and it will never know that a pause frame had been
received. Should it be desirable to know when the MAC
is paused or not, the user should set the PASSALL bit
(MACON1<1>), then manually interpret the pause
control frames which may arrive.
U-0
—
RXPAUS PASSALL MARXEN
BBIPG2
RXEN
Bit 2
r
R-0
r
BBIPG1
FCEN1
Bit 1
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
FCEN1
R/W-0
BBIPG0
FCEN0
Bit 0
—
Values on
FCEN0
R/W-0
Reset
Page:
64
69
69
69
69
69
bit 0