PIC18F96J65-I/PT Microchip Technology, PIC18F96J65-I/PT Datasheet - Page 257

• Manufacturer Part Number: PIC18F96J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.10 Module Resets
The Ethernet module provides selective module
Resets:
• Transmit Only Reset
• Receive Only Reset
18.10.1
Following any standard Reset event, the Ethernet
module returns to a known state. The contents of the
Ethernet buffer memory are unknown. All SFR and
PHY registers are loaded with their specified Reset val-
ues, depending on the type of Reset event. However,
the PHY registers must not be accessed until the PHY
start-up timer has expired and the PHYRDY bit
(ESTAT<0>) becomes set, or at least 1 ms has passed
since the ETHEN bit was set. For more details, see
Section 18.1.3.1 “Start-up Timer”.
© 2009 Microchip Technology Inc.
MICROCONTROLLER RESETS
PIC18F97J60 FAMILY
18.10.2
The Transmit Only Reset is performed by writing a ‘1’
to the TXRST bit (ECON1<7>). This resets the transmit
logic only. Other register and control blocks, such as
buffer management and host interface, are not affected
by a Transmit Only Reset event. To return to normal
operation, the TXRST bit must be cleared in software.
After clearing TXRST, firmware must not write to any
Ethernet module SFRs for at least 1.6 μs. After the
delay, normal operation can resume.
18.10.3
The Receive Only Reset is performed by writing a ‘1’ to
the RXRST bit (ECON1<6>). This action resets receive
logic only. Other register and control blocks, such as the
buffer management and host interface blocks, are not
affected by a Receive Only Reset event. To return to
normal operation, the RXRST bit is cleared in software.
After clearing RXRST, firmware must not write to any
Ethernet module SFRs for at least 1.6 μs. After the
delay, normal operation can resume.
TRANSMIT ONLY RESET
RECEIVE ONLY RESET
DS39762E-page 257