PIC18F96J65-I/PT Microchip Technology, PIC18F96J65-I/PT Datasheet - Page 222

• Manufacturer Part Number: PIC18F96J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
REGISTER 18-8:
18.2.5
The PHY registers provide configuration and control of
the PHY module, as well as status information about its
operation. All PHY registers are 16 bits in width.
PHY registers are accessed with a 5-bit address, for a
total of 32 possible registers; of these, only 7 addresses
are implemented. The implemented registers are listed
in Table 18-3. The main PHY Control registers are
described in Register 18-9 through Register 18-13. The
other PHY Control and Status registers are described
later in this chapter.
Unimplemented registers must never be written to;
reading these locations will return indeterminate data.
Within implemented registers, all reserved bit locations
that are listed as writable must always be written with
the value provided in the register description. When
read, these reserved bits can be ignored.
Thy PHY registers are only accessible through the MII
Management interface. They must not be read or
written to until the PHY start-up timer has expired and
the PHYRDY bit (ESTAT<0>) is set.
18.2.5.1
The PHSTAT1 and PHSTAT2 registers contain
read-only bits that show the current status of the PHY
module’s operations, particularly the conditions of the
communications link to the rest of the network.
DS39762E-page 222
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3
bit 2
bit 1
bit 0
U-0
—
PHY REGISTERS
PHSTAT Registers
Unimplemented: Read as ‘0’
Reserved: Do not use
NVALID: MII Management Read Data Not Valid bit
1 = The contents of the MIRD registers are not valid yet
0 = The MII Management read cycle has completed and the MIRD registers have been updated
SCAN: MII Management Scan Operation bit
1 = MII Management scan operation is in progress
0 = No MII Management scan operation is in progress
BUSY: MII Management Busy bit
1 = A PHY register is currently being read or written to. For internal synchronization, the hardware will
0 = The MII Management interface is Idle
delay setting this bit for two T
bits, or writes to the MIWRH register.
U-0
—
MISTAT: MII STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
CY
U-0
—
following a firmware command which sets the MIISCAN or MIIRD
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
The PHSTAT1 register (Register 18-10) contains the
LLSTAT bit; it clears and latches low if the physical
layer link has gone down since the last read of the
register. The application can periodically poll LLSTAT
to determine exactly when the link fails. It may be
particularly useful if the link change interrupt is not
used.
The PHSTAT2 register (Register 18-12) contains
status bits which report if the PHY module is linked to
the network and whether or not it is transmitting or
receiving.
18.2.5.2
As already mentioned, the PHY registers exist in a
different memory space and are not directly accessible
by the microcontroller. Instead, they are addressed
through a special set of MII registers in the Ethernet
SFR bank that implement a Media Independent
Interface Management (MIIM).
Access is similar to that of the Ethernet buffer, but uses
separate read and write buffers (MIRDH:MIRDL and
MIWRH:MIWRL)
(MIREGADR). In addition, the MICMD and MISTAT
registers are used to control read and write operations.
R-0
r
NVALID
Accessing PHY Registers
R-0
and
© 2009 Microchip Technology Inc.
a
x = Bit is unknown
5-bit
SCAN
R-0
address
BUSY
R-0
register
bit 0