PIC18F96J65-I/PT Microchip Technology, PIC18F96J65-I/PT Datasheet - Page 253

• Manufacturer Part Number: PIC18F96J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.8.5
The Pattern Match filter selects up to 64 bytes from the
incoming packet and calculates an IP checksum of the
bytes. The checksum is then compared to the EPMCS
registers. The packet meets the Pattern Match filter cri-
teria if the calculated checksum matches the EPMCS
registers. The Pattern Match filter may be useful for
filtering packets which have expected data inside them.
To use the Pattern Match filter, the application must
program the Pattern Match offset (EPMOH:EPMOL),
all of the Pattern Match mask bytes (EPMM0:EPMM7)
and the Pattern Match Checksum register pair
(EPMCSH:EPMCSL). The Pattern Match offset should
be loaded with the offset from the beginning of the des-
tination address field to the 64-byte window which will
be used for the checksum computation. Within the
64-byte window, each individual byte can be selectively
included or excluded from the checksum computation
by setting or clearing the respective bit in the Pattern
Match mask. If a packet is received which would cause
the 64 byte window to extend past the end of the CRC,
the filter criteria will immediately not be met, even if the
corresponding mask bits are all ‘0’.
FIGURE 18-14:
© 2009 Microchip Technology Inc.
Note:
Note:
Input Configuration:
EMPOH:EPMOL = 0006h
EPMM7:EPMM0 = 0000000000001F0Ah
EPMCSH:EPMCSL = 563Fh
Received
Data
Byte #
Bytes Used for
Checksum Computation
Values Used for Checksum Computation = {88h, AAh, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 00h}
(00h padding byte added by hardware)
Field
Received data is shown in hexadecimal. Byte numbers are shown in decimal format.
PATTERN MATCH FILTER
In all cases, the value of the Pattern Match
offset must be even for proper operation.
Programming the EMPO register pair with
an odd value will cause unpredictable
results.
11 22 33 44 55 66 77 88 99 AA BB CC 00 5A
0 1 2 3 4 5
SAMPLE PATTERN MATCH FORMAT
DA
6 7 8 9 10 11
SA
Type/Length
64-Byte Window Used
for Pattern Match
12 13
PIC18F97J60 FAMILY
The Pattern Match Checksum registers should be
programmed to the checksum which is expected for the
selected bytes. The checksum is calculated in the
same manner that the DMA module calculates
checksums (see Section 18.9.2 “Checksum Calcula-
tions”). Data bytes which have corresponding mask
bits programmed to ‘0’ are completely removed for
purposes of calculating the checksum, as opposed to
treating the data bytes as zero.
As an example, if the application wished to filter all
packets having a particular source MAC address of
00-04-A3-FF-FF-FF, it could program the Pattern
Match offset to 0000h and then set bits 6 and 7 of
EPMM0 and bits 0, 1, 2 and 3 of EPMM1 (assuming all
other mask bits are ‘0’). The proper checksum to pro-
gram into the EPMCS registers would be 5BFCh. As an
alternative configuration, it could program the offset to
0006h and set bits 0, 1, 2, 3, 4 and 5 of EPMM0. The
checksum would still be 5BFCh. However, the second
case would be less desirable as packets less than
70 bytes long could never meet the Pattern Match cri-
teria, even if they would generate the proper checksum
given the mask configuration.
Another example of a Pattern Match filter is illustrated
in Figure 18-14.
09 0A 0B 0C 0D . . . 40 . . . FE 45 23 01
14 15 16 17 18 . . . 70 . . .
Data
DS39762E-page 253
FCS