PIC18F96J65-I/PT Microchip Technology, PIC18F96J65-I/PT Datasheet - Page 256

• Manufacturer Part Number: PIC18F96J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
18.9.2
The checksum calculation logic treats the source data
as a series of 16-bit big-endian integers. If the source
range contains an odd number of bytes, a padding byte
of 00h is effectively added to the end of the series for
purposes of calculating the checksum.
The calculated checksum is the 16-bit, one’s
complement of the one’s complement sum of all 16-bit
integers. For example, if the bytes included in the
checksum were {89h, ABh, CDh}, the checksum would
begin by computing 89ABh + CD00h. A carry out of the
16th bit would occur in the example, so in 16-bit one’s
complement arithmetic, it would be added back to the
first bit. The resulting value of 56ACh would finally be
complemented to achieve a checksum of A953h.
To calculate a checksum:
1.
2.
3.
TABLE 18-10: SUMMARY OF REGISTERS ASSOCIATED WITH THE DMA CONTROLLER
DS39762E-page 256
EIE
EIR
ECON1
ERXNDL
ERXNDH
EDMASTL
EDMASTH
EDMANDL
EDMANDH
EDMADSTL
EDMADSTH
EDMACSL
EDMACSH
Legend: — = unimplemented. Shaded cells are not used.
Register
Name
Set the EDMAST and EDMAND register pairs to
point to the first and last bytes of buffer data to
be included in the checksum. Care should be
taken when programming these pointers to
prevent a never-ending checksum calculation
due to receive buffer wrapping.
To generate an optional interrupt when the
checksum calculation is done, set the DMAIE
(EIE<5>) and ETHIE (PIE2<5>) bits and clear
the DMAIF (EIR<5>) bit.
Start the calculation by setting the CSUMEN
(ECON1<4>) and DMAST (ECON1<5>) bits.
CHECKSUM CALCULATIONS
Receive End Register Low Byte (ERXND<7:0>)
DMA Start Register Low Byte (EDMAST<7:0>)
DMA End Register Low Byte (EDMAND<7:0>)
DMA Destination Register Low Byte (EDMADST<7:0>)
DMA Checksum Register Low Byte (EDMACS<7:0>)
DMA Checksum Register High Byte (EDMACS<15:8>)
TXRST
Bit 7
—
—
—
—
—
—
RXRST
PKTIE
PKTIF
Bit 6
—
—
—
—
DMAST
DMAIE
DMAIF
Bit 5
—
—
—
—
Receive End Register High Byte (ERXND<12:8>)
DMA Start Register High Byte (EDMAST<12:8>)
DMA End Register High Byte (EDMAND<12:8>)
DMA Destination Register High Byte (EDMADST<12:8>)
CSUMEN
LINKIE
LINKIF
Bit 4
TXRTS
TXIE
Bit 3
TXIF
When the checksum is finished being calculated, the
hardware will clear the DMAST bit, set the DMAIF bit
and an interrupt will be generated if enabled. The DMA
Pointers will not be modified, and no memory will be
written to. The EDMACSH and EDMACSL registers will
contain the calculated checksum. The application may
write this value into a packet, compare this value with
zero (to validate a received block of data containing a
checksum field in it), or compare it with some other
checksum, such as a pseudo header checksum used in
various protocols (TCP, UDP, etc.).
When operating the DMA in Checksum mode, it takes
one instruction cycle (T
the checksum. As a result, if a checksum over
1446 bytes was performed, the DMA module would
require slightly more than 138.8 μs to complete the
operation at 41.667 MHz.
At the same frequency, a small 20-byte header field
would take approximately 1.9 μs plus DMA setup time
to calculate a sum. These estimated times assume that
the Ethernet receive hardware does not need memory
access bandwidth and the CPU does not issue any
reads or writes to the EDATA register while the DMA is
computing.
Like the DMA Copy mode, the checksum operation will
not start until the TXRTS bit (ECON1<3>) is clear. This
may considerably increase the checksum calculation
time if the application transmits a large packet and
immediately attempts to validate a checksum on a
received packet.
RXEN
Bit 2
—
—
TXERIE
TXERIF
Bit 1
—
CY
© 2009 Microchip Technology Inc.
) for every byte included in
RXERIE
RXERIF
Bit 0
—
Values on
Reset
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