PIC18F96J65-I/PT Microchip Technology, PIC18F96J65-I/PT Datasheet - Page 223

• Manufacturer Part Number: PIC18F96J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

To read from a PHY register:
1.
2.
3.
4.
5.
To write to a PHY register:
1.
2.
3.
The PHY register is written after the MII operation
completes, which takes 10.24 μs. When the write
operation has completed, the BUSY bit will clear itself.
The application should not start any MII scan or read
operations while busy.
When a PHY register is written to, the entire 16 bits is
written at once; selective bit and/or byte writes are not
implemented. If it is necessary to reprogram only select
bits in the register, the controller must first read the
PHY register, modify the resulting data and then write
the data back to the PHY register.
© 2009 Microchip Technology Inc.
Write the address of the PHY register to be read
into the MIREGADR register.
Set the MIIRD bit (MICMD<0>). The read
operation begins and the BUSY bit (MISTAT<0>)
is set after two T
Wait 10.24 μs, then poll the BUSY bit to be
certain that the operation is complete. When the
MAC has obtained the register contents, the
BUSY bit will clear itself. While BUSY is set, the
user application should not start any MIISCAN
operations or write to the MIWRH register.
Clear the MIIRD bit.
Read the entire 16 bits of the PHY register from
the MIRDL and MIRDH registers.
Write the address of the PHY register to be
written into the MIREGADR register.
Write the lower 8 bits of data to write into the
MIWRL register.
Write the upper 8 bits of data to write into the
MIWRH register. Writing to this register auto-
matically begins the MII transaction, so it must
be written to after MIWRL. The BUSY bit is set
automatically after two T
CY
.
CY
.
PIC18F97J60 FAMILY
The MAC can also be configured to perform automatic
back-to-back read operations on a PHY register. To
perform this scan operation:
1.
2.
After MIISCAN is set, the NVALID (MISTAT<2>), SCAN
and BUSY bits are also set. The first read operation will
complete after 10.24 μs. Subsequent reads will be
done and the MIRDL and MIRDH registers will be con-
tinuously updated automatically at the same interval
until the operation is cancelled. The NVALID bit may be
polled to determine when the first read operation is
complete.
There is no status information which can be used to
determine when the MIRD registers are updated. Since
only one MII register can be read at a time, it must not
be assumed that the values of MIRDL and MIRDH
were read from the PHY at exactly the same time
during a scan operation.
MIISCAN should remain set as long as the scan
operation is desired. The BUSY and SCAN bits are
automatically cleared after MIISCAN is set to ‘0’ and
the last read sequence is completed. MIREGADR
should not be updated while MIISCAN is set.
Starting new PHY operations, such as a read operation
or writing to the MIWRH register, must not be done
while a scan is underway. The operation can be
cancelled by clearing the MIISCAN bit and then polling
the BUSY bit. New operations may be started after the
BUSY bit is cleared.
Write the address of the PHY register to be
scanned into the MIREGADR register.
Set the MIISCAN bit (MICMD<1>). The scan
operation begins and the BUSY bit is set after
two T
CY
.
DS39762E-page 223