PIC18F96J65-I/PT Microchip Technology, PIC18F96J65-I/PT Datasheet
PIC18F96J65-I/PT
Specifications of PIC18F96J65-I/PT
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PIC18F96J65-I/PT Summary of contents
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... This document includes the programming specifications for the following devices: • PIC18F66J60 • PIC18F66J65 • PIC18F67J60 • PIC18F86J60 • PIC18F86J65 • PIC18F87J60 • PIC18F96J60 • PIC18F96J65 • PIC18F97J60 TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F97J60 FAMILY Pin Name Pin Name MCLR MCLR (1) ...
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... RF2 16 Note: Bold-faced names indicate the pins that are required for programming. For more information, see Table 2-1. DS39688D-page PIC18F66J60 PIC18F66J65 PIC18F67J60 DDRX 48 TPIN+ 47 TPIN SSRX 45 RB4 44 RB5 43 RB6/PGC OSC2 40 OSC1 RB7/PGD 37 RC5 36 RC4 35 RC3 34 RC2 © 2009 Microchip Technology Inc. ...
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... CAP 12 RF7 13 RF6 14 RF5 15 RF4 16 RF3 17 RF2 18 RH7 19 RH6 Note: Bold-faced names indicate the pins that are required for programming. For more information, see Table 2-1. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY PIC18F86J60 PIC18F86J65 PIC18F87J60 DDRX 60 TPIN+ 59 TPIN SSRX 57 RG0 ...
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... RF6 19 RF5 20 RF4 21 RF3 22 RF2 23 RH7 24 RH6 25 Note: Bold-faced names indicate the pins that are required for programming. For more information, see Table 2-1. DS39688D-page 4 PIC18F96J60 PIC18F96J65 PIC18F97J60 © 2009 Microchip Technology Inc DDRX TPIN+ 74 TPIN SSRX RG0 71 RG1 70 RB4 69 RB5 ...
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... These device ID bits read out normally, even after code protection. TABLE 2- Device PIC18F66J60 PIC18F86J60 PIC18F96J60 PIC18F66J65 PIC18F86J65 PIC18F96J65 PIC18F67J60 /V CAP PIC18F87J60 PIC18F97J60 2.2.1 MEMORY ADDRESS POINTER Memory in the device address space (000000h to 3FFFFFh) is addressed via the Table Pointer register, which in turn is comprised of three registers: • ...
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... Read as ‘0’ Configuration Space Configuration Words Configuration Space Device IDs 000000h Code Memory 00FFFFh 017FFFh 01FFFFh Unimplemented Read as ‘0’ 1FFFFFh 200000h Configuration Space 2FFFFFh 300000h Configuration Words 300005h Configuration Space 3FFFFEh Device IDs 3FFFFFh © 2009 Microchip Technology Inc. ...
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... ENTERING PROGRAM/VERIFY MODE P13 MCLR V DD PGD PGC P19 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 2.4 Entering and Exiting ICSP Program/Verify Mode Entry into ICSP modes for PIC18F97J60 family devices is somewhat different than previous PIC18 devices. As shown in Figure 2-7, entering ICSP Program/Verify mode requires three steps: 1 ...
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... Data Payload PGD = Input COMMANDS FOR PROGRAMMING 4-Bit Description Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 SAMPLE COMMAND SEQUENCE Data Core Instruction Payload 3C 40 Table Write, post-increment P5A Fetch Next 4-Bit Command © 2009 Microchip Technology Inc. ...
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... FIGURE 3-2: BULK ERASE TIMING PGC P5 PGD 4-Bit Command 16-Bit Data Payload © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 3-1: 4-Bit Command 0000 0000 0000 0000 0000 0000 1100 0000 0000 0000 0000 0000 0000 1100 0000 0000 FIGURE 3-1: 1 ...
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... Command PGD = Input ROW ERASE CODE MEMORY FLOW Start Addr = 0 Configure Device for Row Erase Start Erase Sequence and Hold PGC High for Time P10 All No Rows Done? Yes Done P10 16-Bit Row-Erase Time Data Payload © 2009 Microchip Technology Inc. ...
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... To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented each iteration of the loop. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY The code sequence to program a PIC18F97J60 family device is shown in Table 3-3. The flowchart shown in Figure 3-5 depicts the logic necessary to completely write a PIC18F97J60 family device ...
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... Write Buffer at <Addr> All No Bytes Written? Yes Start Write Sequence and Hold PGC High Until Done and Wait P9 All No Locations Done? Yes Done P5A 16-Bit Data Payload 4-Bit Command PGD = Input 16-Bit Programming Time Data Payload © 2009 Microchip Technology Inc. ...
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... Step 6: To continue modifying data, repeat Steps 1 through 4, where the Address Pointer is incremented by 1024 bytes at each iteration of the loop. Step 7: Disable writes. 0000 94 A6 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 3.2.2 CONFIGURATION WORD PROGRAMMING Since the Flash Configuration Words are stored in program memory, they are programmed as if they were program data. Refer to Section 3.2 “ ...
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... Configuration registers. Core Instruction MOVLW Addr[21:16] MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL TBLRD *+ P14 LSb Shift Data Out PGD = Output P5A MSb Fetch Next 4-Bit Command PGD = Input © 2009 Microchip Technology Inc. ...
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... Yes All No Code Memory Verified? Yes Done © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 4.3 Blank Check The term “Blank Check” means to verify that the device has no programmed memory cells. All memories must be verified: code memory and Configuration bits. The Device ID registers (3FFFFEh:3FFFFFh) should be ignored ...
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... XXXFEh 300006h XXXFFh 300007h Default/ Bit 1 Bit 0 Unprogrammed Value — WDTEN 111- ---1 — — ---- 01-- FOSC1 FOSC0 11-- -111 WDTPS1 WDTPS0 ---- 1111 — — 1111 1--- (4) (4) CCP2MX ---- -111 REV1 REV0 See Table 5-4 DEV4 DEV3 See Table 5-4 © 2009 Microchip Technology Inc. ...
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... IESO CONFIG2L FCMEN CONFIG2L FOSC2 CONFIG2L FOSC1:FOSC0 CONFIG2L © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Description Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to in-circuit debug ...
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... ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 CCP2 MUX bit 1 = ECCP2/P2A is multiplexed with RC1 0 = ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode (100-pin devices only) © 2009 Microchip Technology Inc. ...
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... DEVICE ID VALUES Device PIC18F66J60 PIC18F66J65 PIC18F67J60 PIC18F86J60 PIC18F86J65 PIC18F87J60 PIC18F96J60 PIC18F96J65 PIC18F97J60 Legend: The ‘x’s in DEVID1 are reserved for the device revision code. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 5-1: READ DEVICE ID WORD FLOW Start Set TBLPTR = 3FFFFE ...
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... SUM[000000:00FFF7] + ([01FFF8] & E1h) + ([01FFF9] & 0Ch) + ([01FFFA] & C7h) + ([01FFFB] & 0Fh) + ([01FFFC] & F8h) + ([01FFFD] & 07h) On 0000h PIC18F96J65 Off SUM[000000:017FF7] + ([01FFF8] & E1h) + ([01FFF9] & 0Ch) + ([01FFFA] & C7h) + ([01FFFB] & 0Fh) + ([01FFFC] & F8h) + ([01FFFD] & 07h) ...
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... Note 1: V must be supplied to the V DDCORE Section 2.1.1 “On-Chip Voltage Regulator” for more information must also be supplied to the AV DD regulator is used. AV and AV DD © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Min Max 2.35 2.70 ENVREG = V V 3.60 SS DDCORE ENVREG = V 2.65 3 ...
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... See DDCORE CAP pins during programming and to the ENVREG if the on-chip voltage DD should always be within ±0. Units Conditions μ and V , respectively. SS © 2009 Microchip Technology Inc. ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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