PIC18F96J65-I/PT Microchip Technology, PIC18F96J65-I/PT Datasheet - Page 444

• Manufacturer Part Number: PIC18F96J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
FIGURE 27-14:
TABLE 27-19: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
DS39762E-page 444
Param
70
71
71A
72
72A
73A
74
75
76
77
80
82
83
Note 1:
No.
Note:
(CKP = 0)
(CKP = 1)
SDI
SDIx
SCKx
SDOx
SSx
SCKx
2:
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
SS
SS
SC
SC
SC
SC
SS
SC
SC
SS
SC
SC
Symbol
B
DO
DO
2
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
L2
Refer to Figure 27-3 for load conditions.
L2
L2
H2
H2
L2
H2
L2
H
L
H2
L2
B
R
F
DO
SC
SC
DO
SS
DI
DO
SS
DO
DI
L
H
L,
V SDOx Data Output Valid after SSx ↓ Edge
H,
L
V
H,
V,
Z SSx ↑ to SDOx Output High-Impedance
SSx ↓ to SCKx ↓ or SCKx ↑ Input
SCKx Input High Time
SCKx Input Low Time
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
Hold Time of SDIx Data Input to SCKx Edge
SDOx Data Output Rise Time
SDOx Data Output Fall Time
SDOx Data Output Valid after SCKx Edge
SSx ↑ after SCKx Edge
82
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
70
MSb In
MSb
74
71
75, 76
Characteristic
72
bit 6 - - - - - - 1
bit 6 - - - - 1
Continuous
Single Byte
Continuous
Single Byte
80
LSb
LSb In
1.25 T
1.25 T
1.5 T
Min
T
100
CY
40
40
CY
10
—
—
—
—
CY
CY
CY
83
+ 40
+ 40
+ 30
+ 30
© 2009 Microchip Technology Inc.
77
Max Units Conditions
25
50
50
50
—
—
—
—
—
—
25
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)