SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 85

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

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These options can be applied regardless of the synthesis tool used.
Depending on your design, some options may have more of an effect than
others.
You can specify synthesis and physical synthesis netlist optimizations in the
Analysis & Synthesis Settings page and Physical Synthesis Optimizations
page of the Settings dialog box.
Netlist optimizations for synthesis include the following options:
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Netlist optimizations for physical synthesis and fitting include the following
groups of options:
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Timing-Driven Synthesis—Directs the Quartus II software to
synthesize your design as directed by timing analysis results from a
previous compilation, where possible.
Perform WYSIWYG primitive resynthesis—Directs the Quartus II
software to unmap WYSIWYG primitives during synthesis. When this
option is turned on, the Quartus II software unmaps the logic elements
in an atom netlist to gates, and remaps the gates to Altera LCELL
primitives. This option allows the Quartus II software to use techniques
specific to a device architecture during the remapping process and uses
the optimization technique (Speed, Balanced, or Area).
Perform register retiming—Allows registers to be moved across
combinational logic to balance timing, but does not change the
functionality of the current design. This option moves registers across
combinational gates only, and not across user-instantiated logic cells,
memory blocks, DSP blocks, or carry or cascade chains, and has the
ability to move registers from the inputs of a combinational logic block
to the block’s output, potentially combining the registers. It can also
create multiple registers at the input of a combinational logic block
from a register at the output of a combinational logic block.
Optimize for performance (physical synthesis)—Options to perform
physical synthesis optimizations on combinational logic, and to
perform register retiming, during fitting.
Effort level—Specifies the level of effort used by the Quartus II
software when performing physical synthesis (Normal, Extra, and
Fast).
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