SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 52

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

A
LTERA
f
C
ORPORATION
The Quartus II logic options that are available on the Analysis & Synthesis
Settings page allow you to specify that the Compiler should optimize for
speed or area, or perform a “balanced” optimization, which attempts to
achieve the best combination of speed and area. It also provides other
options, such as options that control timing-driven synthesis, the logic level
for power-up, and the removal of duplicate or redundant logic.
Using Quartus II Synthesis Netlist
Optimization Options
Quartus II synthesis optimization options allow you to optimize the netlist
during synthesis for many of the Altera device families. These optimization
options are additional to the optimization that occurs during a standard
compilation, and occur during the Analysis & Synthesis stage of a full
compilation. These optimizations make changes to your synthesis netlist
that are generally beneficial for area and speed. The Physical Synthesis
Optimizations page in the Settings dialog box allows you to specify netlist
optimization options.
For more information about synthesis netlist optimization, refer to
Netlist Optimizations to Achieve Timing Closure” on page 142 in Chapter
10, “Timing Closure.”
For Information About
Verilog HDL constructs supported in
the Quartus II software
VHDL constructs supported in the
Quartus II software
Using Quartus II Integrated Synthesis
Using Quartus II logic options to
control synthesis
Creating a logic option assignment
Using Quartus II synthesis options and
logic options that affect synthesis
U
SING
I
NTRODUCTION TO THE
Q
UARTUS
II V
ERILOG
Refer To
“Quartus II Verilog HDL Support” in
Quartus II Help
“Quartus II VHDL Support” in Quartus II
Help
Quartus II Integrated Synthesis chapter in
volume 1 of the Quartus II Handbook
“Working With Assignments in the
Assignment Editor” and “Specifying Default
Logic Options and Parameters” in Quartus II
Help
“Module 3: Compile a Design” in the
Quartus II Interactive Tutorial
Quartus II Integrated Synthesis chapter in
volume 1 of the Quartus II Handbook
HDL & VHDL I
Q
UARTUS
II S
C
HAPTER
NTEGRATED
OFTWARE
3: S
YNTHESIS
S
“Using
YNTHESIS
■
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