SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 17

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

C
C
Table 2. Command-Line Executables (Part 1 of 2)
8
OMMAND
quartus_map
quartus_fit
quartus_drc
quartus_sta
quartus_asm
quartus_eda
quartus_cdb
HAPTER
Executable
Name
■
-L
1: D
I
INE
NTRODUCTION TO THE
ESIGN
E
XECUTABLES
F
Analysis &
Synthesis
Fitter
Design Assistant
TimeQuest Timing
Analyzer
Assembler
EDA Netlist Writer
Compiler
Database Interface
(including VQM
Writer)
LOW
Title
Q
UARTUS
Creates a project if one does not already exist,
and then creates the project database,
synthesizes your design, and performs
technology mapping on design files of the
project.
Places and routes a design. Analysis & Synthesis
must be run successfully before running the
Fitter.
Checks the reliability of a design based on a set
of design rules. Design Assistant is especially
useful for checking the reliability of a design
before migrating the design to HardCopy
devices. Either Analysis & Synthesis or the Fitter
must be run successfully before running the
Design Assistant.
Performs ASIC-style timing analysis of the circuit
using constraints entered in Synopsys Design
Constraint format.
Creates one or more programming files for
programming or configuring the target device.
The Fitter must be run successfully before
running the Assembler.
Generates netlist files and other output files for
use with other EDA tools. Analysis & Synthesis,
the Fitter, or the Timing Analyzer must be run
successfully before running the EDA Netlist
Writer, depending on the options used.
Imports and exports version-compatible
databases and merges partitions. Generates
internal netlist files, including Verilog Quartus
Mapping Files, for the Quartus II Compiler
database so they can be used for
back-annotation and for the LogicLock feature,
and back-annotates device and resource
assignments to preserve the fit for future
compilations. Either the Fitter or Analysis &
Synthesis must be run successfully before
running the Compiler Database Interface.
II S
OFTWARE
Function
A
LTERA
C
ORPORATION