SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 119

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

C
EDA S
Figure 2. Simulation Flow
110
HAPTER
from Quartus II
IMULATION
■
Fitter
8: EDA T
I
NTRODUCTION TO THE
The EDA Netlist Writer module of the Quartus II software generates VHDL
Output Files (.vho) and Verilog Output Files (.vo) for performing functional
or timing simulation, and Standard Delay Format Output Files (.sdo) that
are required for performing timing simulation with EDA simulation tools.
The Quartus II software generates SDF Output Files in Standard Delay
Format version 2.1. The EDA Netlist Writer places simulation output files in
a tool-specific directory under the current project directory.
In addition, the Quartus II software offers seamless integration for timing
simulation with EDA simulation tools through the NativeLink feature. The
NativeLink feature allows the Quartus II software to pass information to
EDA simulation tools, and to launch EDA simulation tools from within the
Quartus II software.
Generating Simulation Output Files
You can run the EDA Netlist Writer module to generate Verilog Output Files
and VHDL Output Files by specifying EDA tool settings and compiling the
design. If you have already compiled a design in the Quartus II software,
you can specify different simulation output settings in the Quartus II
software (for example, a different simulation tool) and then regenerate the
Verilog Output Files or VHDL Output Files by clicking Start EDA Netlist
T
OOLS
OOL
EDA Netlist Writer
quartus_eda
Quartus II
S
UPPORT
Q
UARTUS
II S
Verilog Output
Files, VHDL
Output Files &
test bench files
Verilog Output Files (.vo),
VHDL Output Files (.vho),
Standard Delay Format
Output Files (.sdo) &
test bench files (.vt, .vht)
OFTWARE
Simulation Tool
Simulation Tool
(Functional)
(Timing)
EDA
EDA
A
LTERA
Timing simulation
libraries
Functional
simulation
libraries
C
Test bench files
ORPORATION