SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 102
![QUARTUS II ANNUAL SUBSCRIPTION](/photos/9/32/93247/quartus_ii_sml.jpg)
SW-QUARTUS-SE-FIX
Manufacturer Part Number
SW-QUARTUS-SE-FIX
Description
QUARTUS II ANNUAL SUBSCRIPTION
Manufacturer
Altera
Type
Design Softwarer
Series
QUARTUS IIr
Specifications of SW-QUARTUS-SE-FIX
Mfg Application Notes
Software Licensing App Note
Core Architecture
CPLD, FPGA
Supported Families
Quartus II, Nios II
Software Edition
Standard
License Type
Fixed - Node
Supported Hosts
Windows
Rohs Compliant
NA
For Use With/related Products
Altera Devices
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1247
FIXEDPC
FIXEDPC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SW-QUARTUS-SE-FIX
Manufacturer:
Altera
Quantity:
135
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Using an External Logic Analyzer
A
LTERA
f
f
C
ORPORATION
The Logic Analyzer Interface is logic within the device you use to connect a
large set of internal device signals to a small number of output pins for
debugging purposes. The Logic Analyzer Interface enables you to connect to
and transmit internal signals buried within your FPGA to an external logic
analyzer for analysis. The Logic Analyzer Interface allows you to debug a
large set of internal signals using a small number of output pins. In the
Quartus II Logic Analyzer Interface, the internal signals are grouped
together, distributed to a user-configurable multiplexer, and then output to
available I/O pins on your FPGA. Instead of having a one-to-one
relationship between internal signals to output pins, the Quartus II Logic
Analyzer Interface enables you to map many internal signals to a smaller
number of output pins. The exact number of internal signals that you can
map to an output pin varies based on the multiplexer settings in the Logic
Analyzer Interface.
Logic Analyzer Interface Files (.lai) appear in the Logic Analyzer Interface
Editor window.
For Information About
Using the SignalTap II Logic Analyzer
For Information About
Using External Logic Analyzers
C
HAPTER
I
NTRODUCTION TO THE
7: D
EBUGGING AND
Refer To
Design Debugging Using the SignalTap II
Embedded Logic Analyzer chapter in
volume 3 of the Quartus II Handbook
“About the SignalTap II Logic Analyzer” in
Quartus II Help
“Module 8: SignalTap II Logic Analyzer” in
the Quartus II Interactive Tutorial
Refer To
In-System Debugging Using External Logic
Analyzers chapter in volume 3 of the
Quartus II Handbook
“About the Logic Analyzer Interface Editor”
in Quartus II Help
E
U
NGINEERING
Q
SING AN
UARTUS
E
II S
XTERNAL
C
HANGE
OFTWARE
L
OGIC
M
ANAGMENT
A
■
NALYZER
93
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