SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 106

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

Using the RTL Viewer & Technology
Map Viewer For Debugging
Using the Chip Planner for
Debugging
A
LTERA
f
C
ORPORATION
You can use the RTL Viewer to analyze your design after analysis and
elaboration is complete. The RTL Viewer provides a gate-level schematic
view of your design and a hierarchy list, which lists the instances, primitives,
pins, and nets for the entire design netlist. You can filter the information that
appears in the schematic view and navigate through different pages of the
design view to examine your design and determine what changes should be
made.
The Quartus II Technology Map Viewer provides a low-level, or atom-level,
technology-specific schematic representation of a design. The Technology
Map Viewer includes a schematic view and a hierarchy list, which lists the
instances, primitives, pins, and nets for the entire design netlist.
For more information on using the RTL Viewer and the Technology Map
Viewer, refer to
“The Technology Map Viewer” on page 48
You can use the Chip Planner in conjunction with the SignalTap II Logic
Analyzer and SignalProbe debugging tools to speed up design verification
and incrementally fix bugs uncovered during design verification. After you
run the SignalTap II Logic Analyzer or verify signals with the SignalProbe
feature, you can use the Chip Planner to view details of post-compilation
For Information About
Using the In-System Sources and
Probes Editor
C
“Analyzing Synthesis Results With the Netlist Viewers”
HAPTER
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SING THE
I
NTRODUCTION TO THE
7: D
RTL V
EBUGGING AND
IEWER
& T
Refer To
Design Debugging Using In-System Sources
and Probes chapter in volume 3 of the
Quartus II Handbook
“About the In-System Sources and Probes
Editor” in Quartus II Help
ECHNOLOGY
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in
NGINEERING
Q
UARTUS
Chapter 3, “Synthesis.”
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IEWER
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