SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 32

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

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Using the Quartus II Text Editor
The Text Editor is a flexible tool for entering text-based designs in the
AHDL, VHDL, and Verilog HDL languages, and the Tcl scripting language.
You can also use the Text Editor to enter, edit, and view other ASCII text
files, including those created for or by the Quartus II software.
The Text Editor also allows you to insert a template for any AHDL statement
or section, Tcl command, or supported VHDL or Verilog HDL construct into
the current file. AHDL, VHDL, and Verilog HDL templates provide an easy
way for you to enter HDL syntax, increasing the speed and accuracy of
design entry. You can also get context-sensitive Help on all AHDL elements,
keywords, statements, megafunctions, and primitives.
Using Verilog HDL, VHDL, & AHDL
You can use the Quartus II Text Editor or another text editor to create Text
Design Files, Verilog Design Files, and VHDL Design Files, and combine
them with other types of design files in a hierarchical design.
Verilog Design Files and VHDL Design Files can contain any combination of
Quartus II–supported constructs. They can also contain Altera-provided
logic functions, including primitives and megafunctions, and user-defined
logic functions.
In the Text Editor, you use the Create/Update command on the File menu to
create a Block Symbol File from the current Verilog HDL or VHDL design
file and then incorporate it into a Block Design File. Similarly, you can create
an AHDL Include File that represents a Verilog HDL or VHDL design file
and incorporate it into an Text Design File or another Verilog HDL or VHDL
design file.
For VHDL designs, you can specify the name of a VHDL library for a design
in the Properties dialog box, which is available from the Files page of the
Settings dialog box on the Assignments menu.
For more information on using the Verilog HDL and VHDL languages in the
Quartus II software, see
Integrated Synthesis” on page 41 in Chapter 3, “Synthesis.”
AHDL is a high-level, modular language that is completely integrated into
the Quartus II software. AHDL supports Boolean equation, state machine,
conditional, and decode logic. AHDL also allows you to create and use
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