SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 24

QUARTUS II ANNUAL SUBSCRIPTION

SW-QUARTUS-SE-FIX

Manufacturer Part Number
SW-QUARTUS-SE-FIX
Description
QUARTUS II ANNUAL SUBSCRIPTION
Manufacturer
Altera
Type
Design Softwarer
Series
QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

Mfg Application Notes
Software Licensing App Note
Core Architecture
CPLD, FPGA
Supported Families
Quartus II, Nios II
Software Edition
Standard
License Type
Fixed - Node
Supported Hosts
Windows
Rohs Compliant
NA
For Use With/related Products
Altera Devices
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1247
FIXEDPC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SW-QUARTUS-SE-FIX
Manufacturer:
Altera
Quantity:
135
A
LTERA
f
C
ORPORATION
Using LogicLock Regions
A LogicLock region is defined by its size and location on the device. You can
specify the size and location of a region, or direct the Quartus II software to
create them automatically.
With the LogicLock design flow, you can define a hierarchy for a group of
regions by declaring parent and child regions. The Quartus II software
places child regions completely within the boundaries of a parent region.
You can lock a child module relative to its parent region without
constraining the parent region to a locked location on the device.
You can create and modify LogicLock regions by using the Chip Planner, the
LogicLock Regions Window command on the Assignments menu, the
Hierarchy tab of the Project Navigator, or by using Tcl scripts. All LogicLock
attributes and constraint information (clock settings, pin assignments, and
relative placement information) are stored in the Quartus II Settings File for
the project.
You can also use the LogicLock Regions Properties dialog box to edit
existing LogicLock regions, view information about the LogicLock regions
in the design, and determine which regions contain illegal assignments.
In addition, you can add path-based assignments (based on source and
destination nodes), wildcard assignments, and Fitter priority for path-based
and wildcard assignments to LogicLock regions. Setting the priority allows
you to specify the order in which the Quartus II software resolves conflicting
path-based and wildcard assignments.
For Information About
Using Quartus II incremental
compilation
I
NTRODUCTION TO THE
Refer To
Quartus II Incremental Compilation for
Hierarchical & Team-Based Design chapter
in volume 1 of the Quartus II Handbook
“About Incremental Compilation” in
Quartus II Help
“Module 7: Incremental Compilation” in the
Quartus II Interactive Tutorial
D
ESIGN
Q
UARTUS
M
ETHODOLOGIES AND
C
HAPTER
II S
OFTWARE
1: D
ESIGN
P
LANNING
F
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15

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