SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 82

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

Timing Closure
Figure 5. Timing Closure Flow
A
LTERA
f
C
ORPORATION
from Quartus II
Compiler
The Quartus II software offers a fully integrated timing closure flow that
allows you to meet your timing goals by controlling the synthesis and place
and route of a design. Using the timing closure flow results in faster timing
closure for complex designs, reduced optimization iterations, and automatic
balancing of multiple design constraints.
The timing closure flow allows you to perform an initial compilation, view
design results, and perform further design optimization efficiently. You can
use the Chip Planner to analyze the placement and routing of the design and
make assignments, use the Timing Optimization Advisor to view
recommendations for optimizing your design for timing, use netlist
optimizations on the design after synthesis and during place and route, use
LogicLock region assignments, and use the Design Space Explorer (DSE) to
further optimize the design.
For Information About
Using the Quartus II Technology Map
Viewer
Timing Closure
Performance
Achieved
Yes
Met?
No
C
I
NTRODUCTION TO THE
HAPTER
Optimizations
Figure 5
the Quartus II
Analysis with
Optimization
Chip Planner
5: T
Advisor
Timing
Netlist
IMING
Refer To
Analyzing Designs with Quartus II Netlist
Viewers chapter in volume 1 of the
Quartus II Handbook
shows the timing closure flow.
A
NALYSIS AND
Q
to Quartus II
Compiler
UARTUS
Includes making LogicLock
region, timing & location
assignments
Assignment Entry
II S
D
ESIGN
OFTWARE
T
O
IMING
PTIMIZATION
C
■
LOSURE
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