DSP56F803EVM Freescale Semiconductor, DSP56F803EVM Datasheet - Page 36

KIT EVALUATION FOR DSP56F803

DSP56F803EVM

Manufacturer Part Number
DSP56F803EVM
Description
KIT EVALUATION FOR DSP56F803
Manufacturer
Freescale Semiconductor

Specifications of DSP56F803EVM

Processor To Be Evaluated
56F803
Data Bus Width
16 bit
Interface Type
RS-232, JTAG
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
3.8 Serial Peripheral Interface (SPI) Timing
36
Cycle time
Master
Slave
Enable lead time
Master
Slave
Enable lag time
Master
Slave
Clock (SCLK) high time
Master
Slave
Clock (SCLK) low time
Master
Slave
Data set-up time required for inputs
Master
Slave
Data hold time required for inputs
Master
Slave
Access time (time to data active from high-impedance
state)
Slave
Disable time (hold time to high-impedance state)
Slave
Operating Conditions:
RD, WR
A0–A15
PS, DS,
IRQA
Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service
Characteristic
V
SS
= V
SSA
= 0 V, V
56F803 Technical Data, Rev. 16
Table 3-12 SPI Timing
t
II
t
IRQ
DD
= V
DDA
Symbol
t
t
t
t
t
ELD
ELG
t
= 3.0–3.6V, T
t
CH
DH
t
CL
DS
t
C
A
D
17.6
12.5
24.1
Min
100
4.8
3.7
50
25
25
25
20
0
0
2
A
1
= –40° to +85°C, C
Max
15.2
15
First IRQA Interrupt
Instruction Fetch
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
L
Freescale Semiconductor
50pF, f
Figures 3-18, ,
Figures 3-18, ,
Figures 3-18, ,
Figures 3-18, ,
Figures 3-18, ,
OP
See Figure
Figure
Figure
Figure
Figure
3-20,
3-20,
3-20,
3-20,
3-20,
= 80MHz
3-21
3-21
3-21
3-21
3-21
3-21
3-21
3-21
3-21

Related parts for DSP56F803EVM