DSP56F803EVM Freescale Semiconductor, DSP56F803EVM Datasheet - Page 22

• Manufacturer Part Number: DSP56F803EVM
• Description: KIT EVALUATION FOR DSP56F803
• Manufacturer: Freescale Semiconductor

Specifications of DSP56F803EVM

• Processor To Be Evaluated: 56F803
• Data Bus Width: 16 bit
• Interface Type: RS-232, JTAG
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.3 AC Electrical Characteristics
Timing waveforms in
table. In
22
8. This low-voltage interrupt monitors the V
as V
under transient conditions when V
generated).
9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is
regulator drops below V
be generated unless the external power supply drops below the minimum specified value (3.0V).
10. Power
ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate
is. The internally regulated voltage is typically 100mV less than V
self-regulates.
Figure 3-2
DD
120
180
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in
150
30
90
60
via separate traces. If V
0
–
on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is
the levels of V
Section 3.3
EIC
IDD Digital
, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not
DDA
DDA
drops below V
are tested using the V
>V
20
IH
EIO
IDD Analog
and V
56F803 Technical Data, Rev. 16
DDA
(between the minimum specified V
external power supply. V
IL
EIO
for an input signal are shown.
, an interrupt is generated. Functionality of the device is guaranteed
IDD Total
Freq. (MHz)
IL
DD
40
and V
during ramp-up, until 2.5V is reached, at which time it
DDA
IH
is generally connected to the same potential
levels specified in the DC Characteristics
DD
and the point when the V
60
Table
Freescale Semiconductor
EIO
3-14)
interrupt is
80