DSP56F803EVM Freescale Semiconductor, DSP56F803EVM Datasheet - Page 30

KIT EVALUATION FOR DSP56F803

DSP56F803EVM

Manufacturer Part Number
DSP56F803EVM
Description
KIT EVALUATION FOR DSP56F803
Manufacturer
Freescale Semiconductor

Specifications of DSP56F803EVM

Processor To Be Evaluated
56F803
Data Bus Width
16 bit
Interface Type
RS-232, JTAG
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
3.5.4
3.6 External Bus Asynchronous Timing
30
Operating Conditions:
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
PLL stabilization time
Address Valid to WR Asserted
WR Width Asserted
Wait states = 0
Wait states > 0
WR Asserted to D0–D15 Out Valid
Data Out Hold Time from WR Deasserted
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
RD Deasserted to Address Not Valid
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f
User Manual. ZCLK = f
3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
Phase Locked Loop Timing
Operating Conditions:
Characteristic
Characteristic
3
Table 3-10 External Bus Asynchronous Timing
op
3
2
-40
0
o
o
to +85
V
to 0
SS
= V
o
C
o
C
SSA
= 0 V, V
V
56F803 Technical Data, Rev. 16
Table 3-9 PLL Timing
SS
= V
DD
1
SSA
= V
= 0 V, V
DDA
Symbol
t
t
t
Symbol
t
t
t
ARDD
AWR
t
WRD
DOH
DOS
RDA
WR
f
= 3.0–3.6 V, T
out
f
t
t
osc
plls
plls
DD
/2
= V
DDA
(T*WS) + 18.7
(T*WS) + 7.5
(T*WS) + 6.4
out
Min
40
A
= 3.0–3.6 V, T
4
/2, please refer to the OCCS chapter in the
= –40° to +85°C, C
18.7
Min
6.5
7.5
4.8
2.2
0
Typ
100
8
1
A
= –40° to +85°C
1, 2
L
Max
50pF, f
4.2
Freescale Semiconductor
Max
110
200
10
10
op
= 80MHz
MHz
MHz
Unit
ms
ms
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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