DSP56F803EVM Freescale Semiconductor, DSP56F803EVM Datasheet - Page 3

• Manufacturer Part Number: DSP56F803EVM
• Description: KIT EVALUATION FOR DSP56F803
• Manufacturer: Freescale Semiconductor

Specifications of DSP56F803EVM

• Processor To Be Evaluated: 56F803
• Data Bus Width: 16 bit
• Interface Type: RS-232, JTAG
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor
56F803 General Description
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*
includes TCS pin which is reserved for factory use and is tied to VSS
3
3
4
4
2
2
2
4
4
Up to 40 MIPS at 80MHz core frequency
DSP and MCU functionality in a unified,
C-efficient architecture
Hardware DO and REP loops
MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
31.5K × 16-bit words (64KB) Program Flash
512 × 16-bit words (1KB) Program RAM
4K × 16-bit words (8KB) Data Flash
2K × 16-bit words (4KB) Data RAM
2K × 16-bit words (4KB) Boot Flash
Up to 64K × 16-bit words each of external Program
and Data memory
6
Current Sense Inputs
Fault Inputs
A/D1
A/D2
Quad Timer B
PWM Outputs
Quad Timer A
Quad Timer C
Quad Timer D
CAN 2.0A/B
VREF
Decoder 0 /
Quadrature
GPIO
GPIO
SCI
SPI
or
or
ADC
tion-Specific
Peripherals
Program Memory
32252 x 16 Flash
2048 x 16 SRAM
Memory &
512 x 16 SRAM
2048 x 16 Flash
4096 x 16 Flash
Applica-
Data Memory
Boot Flash
Watchdog
Controller
PWMA
Interrupt
COP/
RESET
Hardware Looping Unit
•
MODULE CONTROLS
ADDRESS BUS [8:0]
Program Controller
DATA BUS [15:0]
56F803 Technical Data, Rev. 16
IRQA
56F803 Block Diagram
•
COP RESET
•
and
IRQB
EXTBOOT
CGDB
XAB1
XAB2
XDB2
PDB
PAB
INTERRUPT
CONTROLS
6
JTAG/
OnCE
Port
Generation
•
Address
Unit
•
IPBus Bridge
16
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•
•
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•
•
•
(IPBB)
•
CONTROLS
VCAPC V
2
IPBB
6-channel PWM module
Two 4-channel 12-bit ADCs
Quadrature Decoder
CAN 2.0 B module
Serial Communication Interface (SCI)
Serial Peripheral Interface (SPI)
Up to two General Purpose Quad Timers
JTAG/OnCE
16 shared GPIO lines
100–pin LQFP package
Three 16-bit Input Registers
16 x 16 + 36 → 36-Bit MAC
Two 36-bit Accumulators
6
16
Digital Reg
•
DD
Data ALU
6*
16-Bit
56800
V
Low Voltage
Core
Supervisor
SS
Interface
TM
External
Bus
Unit
V
port for debugging
DDA
Analog Reg
Manipulation
Address Bus
Clock Gen
V
Data Bus
External
External
Control
SSA
Switch
Switch
PLL
Bus
Unit
Bit
6
16
10
A[00:05]
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
D[00:15]
PS Select
DS Select
WR Enable
RD Enable
EXTAL
CLKO
XTAL
3