DSP56F803EVM Freescale Semiconductor, DSP56F803EVM Datasheet - Page 11

• Manufacturer Part Number: DSP56F803EVM
• Description: KIT EVALUATION FOR DSP56F803
• Manufacturer: Freescale Semiconductor

Specifications of DSP56F803EVM

• Processor To Be Evaluated: 56F803
• Data Bus Width: 16 bit
• Interface Type: RS-232, JTAG
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.3 Clock and Phase Locked Loop Signals
2.4 Address, Data, and Bus Control Signals
Freescale Semiconductor
No. of
No. of
Pins
Pins
1
1
1
6
2
8
GPIOE2
GPIOA0
GPIOE3
GPIOA7
A8–A15
EXTAL
A0–A5
A6–A7
Signal
Signal
CLKO
Name
Name
XTAL
–
–
Input/O
Input/O
Signal
Output
Output
Output
Signal
Output
Output
Type
utput
utput
Input/
Type
Input
State During
State During
Chip-driven
Chip-driven
Tri-stated
Tri-stated
Tri-stated
Reset
Input
Input
Reset
Input
Table 2-6 Address Bus Signals
Table 2-5 PLL and Clock
56F803 Technical Data, Rev. 16
Address Bus—A0–A5 specify the address for external Program or Data
memory accesses.
Address Bus—A6–A7 specify the address for external Program or Data
memory accesses.
Port E GPIO—These two pins are General Purpose I/O (GPIO) pins that
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
Address Bus—A8–A15 specify the address for external Program or
Data memory accesses.
Port A GPIO—These eight pins are General Purpose I/O (GPIO) pins
that can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
External Crystal Oscillator Input—This input should be connected to
an 8MHz external crystal or ceramic resonator. For more information,
please refer to
Crystal Oscillator Output—This output should be connected to an
8MHz external crystal or ceramic resonator. For more information,
please refer to
This pin can also be connected to an external clock source. For more
information, please refer to
Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select Register
(CLKOSR), the user can select between outputting a version of the
signal applied to XTAL and a version of the device’s master clock at the
output of the PLL. The clock frequency on this pin can also be disabled
by programming the CLKOSEL[4:0] bits in CLKOSR.
Section
Section
3.5.
3.5.
Signal Description
Signal Description
Section
3.5.3.
Clock and Phase Locked Loop Signals
11