5.07.01 FLASHER ARM Segger Microcontroller Systems, 5.07.01 FLASHER ARM Datasheet - Page 56

• Manufacturer Part Number: 5.07.01 FLASHER ARM
• Description: PROGRAMMER JTAG FOR ARM CORES
• Manufacturer: Segger Microcontroller Systems
• Type: In-System Programmerr

Specifications of 5.07.01 FLASHER ARM

• Contents: Programmer
• For Use With/related Products: ARM7, ARM9, Cortex
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 899-1002

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Flasher ARM (UM08007)
Adaptive clocking
A technique in which a clock signal is sent out by Flasher ARM. Flasher ARM waits for
the returned clock before generating the next clock pulse. The technique allows the
Flasher ARM interface unit to adapt to differing signal drive capabilities and differing
cable lengths.
Big-endian
Memory organization where the least significant byte of a word is at a higher address
than the most significant byte. See Little-endian.
Cache cleaning
The process of writing dirty data in a cache to main memory.
Coprocessor
An additional processor that is used for certain operations, for example, for floating-
point math calculations, signal processing, or memory management.
Dirty data
When referring to a processor data cache, data that has been written to the cache
but has not been written to main memory is referred to as dirty data. Only write-back
caches can have dirty data because a write-through cache writes data to the cache
and to main memory simultaneously. See also cache cleaning.
EmbeddedICE
The additional hardware provided by ARM7/9 processors to aid debugging.
Halfword
A 16-bit unit of information.
Host
A computer which provides data and other services to another computer. Especially, a
computer providing debugging services to a target being debugged.
ICache
Instruction cache.
ID
Identifier.
IEEE 1149.1
The IEEE Standard which defines TAP. Commonly (but incorrectly) referred to as
JTAG.
Image
An executable file that has been loaded onto a processor for execution.
Instruction Register
When referring to a TAP controller, a register that controls the operation of the TAP.
IR
See Instruction Register.
Joint Test Action Group (JTAG)
The name of the standards group which created the IEEE 1149.1 specification.
Little-endian
Memory organization where the least significant byte of a word is at a lower address
than the most significant byte. See also Big-endian.
CHAPTER 8
© 2004-2009 SEGGER Microcontroller GmbH & Co. KG
Glossary