5.07.01 FLASHER ARM Segger Microcontroller Systems, 5.07.01 FLASHER ARM Datasheet - Page 42

• Manufacturer Part Number: 5.07.01 FLASHER ARM
• Description: PROGRAMMER JTAG FOR ARM CORES
• Manufacturer: Segger Microcontroller Systems
• Type: In-System Programmerr

Specifications of 5.07.01 FLASHER ARM

• Contents: Programmer
• For Use With/related Products: ARM7, ARM9, Cortex
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 899-1002

42
5.1
5.1.1
Flasher ARM (UM08007)
Flasher ARM has a JTAG connector compatible with
ARM’s Multi-ICE. The JTAG connector is a 20 way
Insulation Displacement Connector (IDC) keyed box
header (2.54mm male) that mates with IDC sockets
mounted on a ribbon cable.
The following table lists the Flasher ARM JTAG
pinout.
Table 5.1: Flasher ARM pinout
Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in Flasher ARM.
They should also be connected to GND in the target system.
11
13
15
17
19
PIN
1
2
3
5
7
9
JTAG Connector
Pinout
VTref
Vsupply
nTRST
TDI
TMS
TCK
RTCK
TDO
RESET
DBGRQ
5V-Tar-
get sup-
ply
SIGNAL
Input
NC
Output
Output
Output
Output
Input
Input
I/O
NC
Output
TYPE
This is the target reference voltage. It is used to check if
the target has power, to create the logic-level reference for
the input comparators and to control the output logic levels
to the target. It is normally fed from Vdd of the target board
and must not have a series resistor.
This pin is not connected in Flasher ARM. It is reserved for
compatibility with other equipment. Connect to Vdd or leave
open in target system.
JTAG Reset. Output from Flasher ARM to the Reset signal of
the target JTAG port. Typically connected to nTRST of the
target CPU. This pin is normally pulled HIGH on the target
to avoid unintentional resets when there is no connection.
JTAG data input of target CPU. It is recommended that this
pin is pulled to a defined state on the target board. Typically
connected to TDI of target CPU.
JTAG mode set input of target CPU. This pin should be
pulled up on the target. Typically connected to TMS of tar-
get CPU.
JTAG clock signal to target CPU. It is recommended that this
pin is pulled to a defined state of the target board. Typically
connected to TCK of target CPU.
Return test clock signal from the target. Some targets must
synchronize the JTAG inputs to internal clocks. To assist in
meeting this requirement, you can use a returned, and
retimed, TCK to dynamically control the TCK rate. Flasher
ARM supports adaptive clocking, which waits for TCK
changes to be echoed correctly before making further
changes. Connect to RTCK if available, otherwise to GND.
JTAG data output from target CPU. Typically connected to
TDO of target CPU.
Target CPU reset signal. Typically connected to the RESET
pin of the target CPU, which is typically called "nRST",
"nRESET" or "RESET".
This pin is not connected in Flasher ARM. It is reserved for
compatibility with other equipment to be used as a debug
request signal to the target system. Typically connected to
DBGRQ if available, otherwise left open.
This pin is used to supply power to some eval boards. Typi-
cally left open on target hardware.
CHAPTER 5
© 2004-2009 SEGGER Microcontroller GmbH & Co. KG
Description
VTref
nTRST
TDI
TMS
TCK
RTCK
TDO
RESET
DBGRQ
V5-Supply
11
13
15
17
19
1
3
5
7
9
12
2
4
6
8
10
14
16
18
20
Vsupply
GND
GND
GND
GND
GND
GND
GND
GND
GND
Hardware