C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 87

BOARD PROTOTYPE W/C8051F530

C8051F530-TB

Manufacturer Part Number
C8051F530-TB
Description
BOARD PROTOTYPE W/C8051F530
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F530-TB

Contents
Board
Processor To Be Evaluated
C8051F52xA and C8051F53xA
Interface Type
USB
Lead Free Status / RoHS Status
Vendor undefined / Vendor undefined
For Use With/related Products
C8051F530
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
SFR Definition 8.1. SP: Stack Pointer
SFR Definition 8.2. DPL: Data Pointer Low Byte
SFR Definition 8.3. DPH: Data Pointer High Byte
Bits7–0: SP: Stack Pointer.
Bits7–0: DPL: Data Pointer Low.
Bits7–0: DPH: Data Pointer High.
R/W
R/W
R/W
Bit7
Bit7
Bit7
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.
R/W
R/W
R/W
Bit6
Bit6
Bit6
R/W
R/W
R/W
Bit5
Bit5
Bit5
C8051F52x/F52xA/F53x/F53xA
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.3
R/W
R/W
R/W
Bit3
Bit3
Bit3
R/W
R/W
R/W
Bit2
Bit2
Bit2
R/W
R/W
R/W
Bit1
Bit1
Bit1
SFR Address: 0x82
SFR Address: 0x83
SFR Address: 0x81
R/W
R/W
R/W
Bit0
Bit0
Bit0
00000000
00000000
Reset Value
Reset Value
Reset Value
00000111
87

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