C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 158
C8051F530-TB
Manufacturer Part Number
C8051F530-TB
Description
BOARD PROTOTYPE W/C8051F530
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F530-TB.pdf
(218 pages)
Specifications of C8051F530-TB
Contents
Board
Processor To Be Evaluated
C8051F52xA and C8051F53xA
Interface Type
USB
Lead Free Status / RoHS Status
Vendor undefined / Vendor undefined
For Use With/related Products
C8051F530
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F52x/F52xA/F53x/F53xA
SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate
158
Bits7–0: SCR7–SCR0: SPI0 Clock Rate.
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
SCR7
R/W
Bit7
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.
for 0 <= SPI0CKR <= 255
SCR6
f
SCK
R/W
Bit6
f
SCK
f
SCK
=
=
=
200kHz
------------------------- -
2
SCR5
------------------------------------------------ -
2
2000000
R/W
Bit5
4
SPI0CKR
SYSCLK
+
1
SCR4
R/W
Bit4
+
1
Rev. 1.3
SCR3
R/W
Bit3
SCR2
R/W
Bit2
SCR1
R/W
Bit1
SFR Address: 0xA2
SCR0
R/W
Bit0
00000000
Reset Value
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