C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 7

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

List of Figures
Figure 1.1. C8051F53xA Block Diagram ................................................................. 16
Figure 1.2. C8051F52xA Block Diagram ................................................................. 16
Figure 1.3. C8051F53x Block Diagram ................................................................... 17
Figure 1.4. C8051F52x Block Diagram ................................................................... 17
Figure 1.5. Development/In-System Debug Diagram .............................................. 19
Figure 1.6. Memory Map ......................................................................................... 20
Figure 1.7. 12-Bit ADC Block Diagram .................................................................... 22
Figure 1.8. Comparator Block Diagram ................................................................... 23
Figure 1.9. Port I/O Functional Block Diagram ........................................................ 24
Figure 2.1. Typical Active Mode Current vs. Frequency .......................................... 28
Figure 2.2. Typical Idle Mode Current vs. Frequency .............................................. 28
Figure 3.1. DFN-10 Package Diagram .................................................................... 38
Figure 3.2. DFN-10 Landing Diagram ..................................................................... 39
Figure 3.3. TSSOP-20 Package Diagram ............................................................... 43
Figure 3.4. TSSOP-20 Landing Diagram ................................................................. 44
Figure 3.5. QFN-20 Package Diagram* ................................................................... 48
Figure 3.6. QFN-20 Landing Diagram* .................................................................... 50
Figure 4.1. ADC0 Functional Block Diagram ........................................................... 52
Figure 4.2. Typical Temperature Sensor Transfer Function .................................... 53
Figure 4.3. ADC0 Tracking Modes .......................................................................... 55
Figure 4.4. 12-Bit ADC Tracking Mode Example ..................................................... 56
Figure 4.5. 12-Bit ADC Burst Mode Example with Repeat Count Set to 4 .............. 58
Figure 4.6. ADC0 Equivalent Input Circuits ............................................................. 60
Figure 4.7. ADC Window Compare Example: Right-Justified Single-Ended Data .. 71
Figure 4.8. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 71
Figure 5.1. Voltage Reference Functional Block Diagram ....................................... 72
Figure 6.1. External Capacitors for Voltage Regulator Input/Output ....................... 74
Figure 7.1. Comparator Functional Block Diagram ................................................. 76
Figure 7.2. Comparator Hysteresis Plot .................................................................. 77
Figure 8.1. CIP-51 Block Diagram ........................................................................... 81
Figure 9.1. Memory Map ......................................................................................... 92
Figure 11.1. Reset Sources ................................................................................... 106
Figure 11.2. Power-On and V
Figure 12.1. Flash Program Memory Map ............................................................. 116
Figure 13.1. Port I/O Functional Block Diagram .................................................... 119
Figure 13.2. Port I/O Cell Block Diagram .............................................................. 120
Figure 13.3. Crossbar Priority Decoder with No Pins Skipped 
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped
Figure 13.5. Crossbar Priority Decoder with No Pins Skipped (DFN 10) .............. 123
Figure 13.6. Crossbar Priority Decoder with Some Pins Skipped (DFN 10) ......... 124
Figure 14.1. Oscillator Diagram ............................................................................. 134
(TSSOP 20 and QFN 20) ................................................................................. 121
(TSSOP 20 and QFN 20) ................................................................................. 122
DD
C8051F52x/F52xA/F53x/F53xA
Monitor Reset Timing ........................................ 107
Rev. 1.3
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