C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 190

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F52x/F52xA/F53x/F53xA
18.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 18.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
190
T2MH
0
0
1
External Clock / 8
SYSCLK / 12
T2XCLK
0
1
X
T2XCLK
0
1
TMR2H Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK
SYSCLK
Figure 18.5. Timer 2 8-Bit Mode Block Diagram
0
1
1
0
M
H
T
3
T
M
3
L
CKCON
M
T
H
2
M
T
2
L
M
T
1
M
T
0
TR2
S
C
A
1
S
C
A
0
Rev. 1.3
TCLK
TCLK
TMR2RLH
TMR2RLL
T2ML
0
0
1
TMR2H
TMR2L
Reload
Reload
T2XCLK
0
1
X
T2SPLIT
TF2LEN
T2XCLK
TF2H
TF2L
TR2
TMR2L Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK
Interrupt