C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 109

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SFR Definition 11.1. VDDMON: V
11.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 2.7 on page 32 for complete
RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
11.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The state of the RST pin is unaffected by this reset.
11.5. Comparator Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
Bit7:
Bit6:
Bit5:
Bits4–0: RESERVED. Read = Variable. Write = don’t care.
VDMEN VDDSTAT VDMLVL Reserved Reserved Reserved Reserved Reserved 1v000000
R/W
Bit7
VDMEN: V
This bit turns the V
resets until it is also selected as a reset source in register RSTSRC (SFR Definition 11.2).
The V
ing the V
reset. See Table 2.7 on page 32 for the minimum V
0: V
1: V
VDDSTAT: V
This bit indicates the current power supply status (V
0: V
1: V
VDMLVL: V
0: V
1: V
includes code that writes to and/or erases Flash.
DD
DD
DD
DD
DD
DD
Bit6
DD
R
Monitor Disabled.
Monitor Enabled (default).
is at or below the V
is above the V
Monitor Threshold is set to V
Monitor Threshold is set to V
Monitor can be allowed to stabilize before it is selected as a reset source. Select-
DD
DD
DD
monitor as a reset source before it has stabilized may generate a system
DD
Monitor Enable.
Level Select.
Status.
R/W
Bit5
DD
DD
monitor circuit on/off. The V
Monitor Threshold.
DD
Bit4
C8051F52x/F52xA/F53x/F53xA
R
Monitor Threshold.
DD
Monitor Control
RST-LOW
RST-HIGH
Rev. 1.3
Bit3
R
. This setting is required for any system that
(default).
DD
Bit2
R
DD
DD
Monitor cannot generate system
Monitor turn-on time.
Monitor output).
Bit1
R
SFR Address:
Bit0
R
Reset Value
0xFF
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