C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 51
C8051F530-TB
Manufacturer Part Number
C8051F530-TB
Description
BOARD PROTOTYPE W/C8051F530
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F530-TB.pdf
(218 pages)
Specifications of C8051F530-TB
Contents
Board
Processor To Be Evaluated
C8051F52xA and C8051F53xA
Interface Type
USB
Lead Free Status / RoHS Status
Vendor undefined / Vendor undefined
For Use With/related Products
C8051F530
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 3.9. QFN-20 Landing Diagram Dimensions
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise
2. This land pattern design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD).
4. A stainless steel, laser-cut and electro-polished stencil with
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all
7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-
Symbol
noted.
Clearance between the solder mask and the metal pad is to be
60 µm minimum, all the way around the pad.
trapezoidal walls should be used to assure good solder paste
release.
perimeter pads.
used for the center ground pad.
020 specification for Small Body Components.
C1
C2
X1
X2
Y1
Y2
E
C8051F52x/F52xA/F53x/F53xA
Rev. 1.3
3.90
3.90
0.20
2.75
0.65
2.75
Min
0.50 BSC.
Max
4.00
4.00
0.30
2.85
0.75
2.85
51
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