C8051F411EK Silicon Laboratories Inc, C8051F411EK Datasheet - Page 268
![KIT EVAL FOR C8051F411](/photos/9/25/92547/c8051f411ek_sml.jpg)
C8051F411EK
Manufacturer Part Number
C8051F411EK
Description
KIT EVAL FOR C8051F411
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F411EK
Contents
Evaluation Board, CD-ROM, USB Cable, Batteries and User Guide
Processor To Be Evaluated
C8051F41x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F411
Silicon Family Name
C8051F41x
Kit Contents
LCD Based Evaluation Board, USB Cable, Software CD And Quick-Start Guide
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F41x
For Use With
336-1315 - KIT REF DESIGN VOICE RECORD F41X
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1317
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C8051F410/1/2/3
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Revision 0.7 to Revision 0.8
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Revision 0.8 to Revision 1.0
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Revision 1.0 to Revision 1.1
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268
OCUMENT
Updated specification tables with most recently available characterization data.
Corrected references to configuring pins for Analog Mode - Port Latch must contain a '1'.
SFR Definition 5.6: Address correction to 0xBA.
Added Figure 8.2 showing power connection diagram without using on-chip regulator.
Section 9
Table 11.2 : Corrected SFR Name P2MDIN on location 0xF3.
Section 14
Section 18
last sentence.
Section 19.2.2
Section 19.3
cies.
Section 21
Table 21.4 : Made corrections to SMBus state descriptions.
Figure 24.6 : Corrected T2RCLK Mux selection options.
Figure 24.9 : Corrected T3RCLK Mux selection options.
C2 Register Definition 26.2 : Corrected DEVICEID value to 0x0C.
Updated specification tables with full characterization data.
Updated Flash write and erase procedures to include a write to FLSCL.3-0.
Changed /RST pin comments in Table 4.1, “Pin Definitions for the C8051F41x,” on page 41 for the recom-
mended pull-up resistor.
Changed the reset value of the SFR Definition 16.3. FLSCL: Flash Scale.
Removed the "Optional GND Connection" from Figure 4.5. ’Typical QFN-28 Landing Diagram’ on page 48.
Added a note regarding the maximum SYSCLK frequency to SFR Definition 19.4. CLKMUL: Clock Multi-
plier Control.
Updated Figure 4.3. ’LQFP-32 Package Diagram’ on page 46, Figure 4.5. ’QFN-28 Package Drawing’ on
page 48, and Figure 4.6. ’QFN-28 Recommended PCB Land Pattern’ on page 49.
Added note that VIO must be > VDD in Table 3.1, “Global DC Electrical Characteristics,” on page 36.
Added information about ADC0 output register auto-clearing in SFR Definition 5.2.
Corrected ADC0 Tracking time equation in SFR Definition 5.6.
Clarified Voltage Regulator Electrical Specifications in Table 8.1 on page 82.
Added information about 16-bit and 32-bit CRC algorithms in
: Removed references to "High Speed Analog Mode".
, Important Note on page 151 : Added "and have the same behavior as P0 in Normal Mode." to
: Corrected SMBus maximum rate to 1/20th system clock.
: Corrected operational description of CRC engine.
: Added Figure 19.3 and text to describe behavior of clock multiplier with slower input frequen-
C
: Inserted Step 3 "Release the crystal pins by writing ‘1's to the port latch."
HANGE
L
IST
Rev. 1.1
Section 14
.
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