C8051F411EK Silicon Laboratories Inc, C8051F411EK Datasheet - Page 221
![KIT EVAL FOR C8051F411](/photos/9/25/92547/c8051f411ek_sml.jpg)
C8051F411EK
Manufacturer Part Number
C8051F411EK
Description
KIT EVAL FOR C8051F411
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F411EK
Contents
Evaluation Board, CD-ROM, USB Cable, Batteries and User Guide
Processor To Be Evaluated
C8051F41x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F411
Silicon Family Name
C8051F41x
Kit Contents
LCD Based Evaluation Board, USB Cable, Software CD And Quick-Start Guide
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F41x
For Use With
336-1315 - KIT REF DESIGN VOICE RECORD F41X
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1317
- Current page: 221 of 270
- Download datasheet (2Mb)
The shift register contents are locked after the slave detects the first edge of SCK. Writes to SPI0DAT that
occur after the first SCK edge will be held in the TX latch until the end of the current transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS sig-
nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 23.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is not a way
of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPI0 with the SPIEN bit. Figure 23.3 shows a connection diagram between a slave device in 3-
wire slave mode and a master device.
23.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
Note that all of the following interrupt bits must be cleared by software.
23.5. Serial Clock Timing
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between a rising edge or a falling edge.
Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should
be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The clock
and data line relationships are shown in Figure 23.5.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 23.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
1. The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This
2. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted
3. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master
4. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave,
flag can occur in all SPI0 modes.
when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the
write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur
in all SPI0 modes.
in multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN
and SPIEN bits are set to logic 0 to disable SPI0 and allow another master device to access
the bus.
and a transfer is completed while the receive buffer still holds an unread byte from a previous
transfer. The new byte is not transferred to the receive buffer, allowing the previously received
data byte to be read. The data byte which caused the overrun is lost.
Rev. 1.1
C8051F410/1/2/3
221
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