Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 94
![KIT DEVELOPMENT F083A](/photos/9/25/92520/z8f083a0128zcog_sml.jpg)
Z8F083A0128ZCOG
Manufacturer Part Number
Z8F083A0128ZCOG
Description
KIT DEVELOPMENT F083A
Manufacturer
Zilog
Series
Z8 Encore! XP®r
Type
MCUr
Specifications of Z8F083A0128ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F083A
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4672
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F083A0128ZCOG
Manufacturer:
Zilog
Quantity:
1
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Table 54. Timer 0–1 Control Register 1 (TxCTL1)
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
TEN
R/W
7
0
TMODEHI—Timer mode high bit
This bit along with the TMODE field in TxCTL1 register determines the operating mode
of the timer. This is the most significant bit of the timer mode selection value. For more
details, see
TICONFIG—Timer interrupt configuration
This field configures timer interrupt definition.
PWMD—PWM delay value
This field is a programmable delay to control the number of system clock cycles delay
before the timer output and the timer output complement are forced to their active state.
•
•
•
•
•
•
•
•
INPCAP—Input Capture event
This bit indicates whether the most recent timer interrupt is caused by a timer input
Capture event.
Timer 0–1 Control Register 1
The timer 0–1 control (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
0x = Timer interrupt occurs on all the defined reload, compare and input events.
10 = Timer interrupt occurs only on defined input Capture/Deassertion events.
11 = Timer interrupt occurs only on defined Reload/Compare events.
000 = No delay
001 = 2 cycles delay
010 = 4 cycles delay
011 = 8 cycles delay
100 = 16 cycles delay
101 = 32 cycles delay
110 = 64 cycles delay
111 = 128 cycles delay
0 = Previous timer interrupt is not caused by timer input Capture event
1 = Previous timer interrupt is caused by timer input Capture event
TPOL
R/W
6
0
Timer 0–1 Control Register 1
R/W
5
0
PRES
R/W
4
0
F07H, F0FH
on page 82.
R/W
3
0
R/W
Z8 Encore!
2
0
Product Specification
TMODE
R/W
1
0
®
F083A Series
R/W
0
0
Timers
82
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