Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 42

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

Table 11. Reset Status Register (RSTSTAT)
Debug Pin Driven Low
Reset Register Definitions
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
Reset or Stop Mode Recovery Event
Power-On Reset
Reset using RESET pin assertion
Reset using WDT time-out
Reset using the On-Chip Debugger (OCTCTL[1] set to 1)
Reset from STOP mode using DBG pin driven Low
Stop Mode Recovery using GPIO pin transition
Stop Mode Recovery using WDT time-out
Reset Status Register
POR
R
7
Debug reset is initiated when the On-Chip Debugger detects any of the following error
conditions on the DBG pin:
•
•
•
When the Z8F083 is in STOP mode, the debug reset will cause a system reset. The On-
Chip Debugger block is not reset, but the rest of the chip goes through a normal system
reset. The POR bit in the reset (RSTSTAT) register is set to 1.
The reset status (RSTSTAT) register detailed in
indicates the source of the most recent Reset event, a Stop Mode Recovery event, or a
WDT time-out event. Reading this register resets the upper four bits to 0.
This register shares its address with the Watchdog timer control register, which is write-
only.
See descriptions below
Serial break (a minimum of nine continuous bits low)
Framing error (received STOP bit is low)
Transmit collision (OCD and host simultaneous transmission detected by the OCD)
STOP
R
6
WDT
R
5
EXT
R
4
0
FF0H
R
3
0
Table 11
POR
1
0
0
1
1
0
0
is a read-only register that
Z8 Encore!
R
2
0
Reset and Stop Mode Recovery
Reserved
STOP
Product Specification
0
0
0
0
0
1
1
R
1
0
®
WDT
F083A Series
0
0
1
0
0
0
1
EXT
R
0
0
0
1
0
0
0
0
0
30