Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 70

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

Table 32. Interrupt Request 0 Register (IRQ0)
Table 33. Interrupt Request 1 Register (IRQ1)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
Interrupt Request 1 Register
Reserved
PA7I
R/W
R/W
7
0
7
0
CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the
interrupt request 0 register to determine if any interrupt requests are pending.
Reserved—Must be 0.
T1I—Timer 1 interrupt request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from timer 1 is awaiting service.
T0I—Timer 0 interrupt request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from timer 0 is awaiting service.
ADCI—ADC interrupt request
0 = No interrupt request is pending for the ADC.
1 = An interrupt request from the ADC is awaiting service.
The interrupt request 1 (IRQ1) register stores interrupt requests for both vectored and
polled interrupts. See
corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the interrupt request
1 register to determine if any interrupt requests are pending.
PA6CI
R/W
R/W
T1I
6
0
6
0
PA5I
R/W
Table
R/W
T0I
5
0
5
0
33. When a request is sent to the interrupt controller, the
Reserved Reserved Reserved Reserved
PA4I
R/W
R/W
4
0
4
0
FC0H
FC3H
PA3I
R/W
R/W
3
0
3
0
PA2I
R/W
R/W
Z8 Encore!
2
0
2
0
Product Specification
PA1I
R/W
R/W
1
0
1
0
®
Interrupt Controller
F083A Series
ADCI
PA0I
R/W
R/W
0
0
0
0
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