Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 40

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

Stop Mode Recovery
PS026308-1207
External Reset Indicator
On-Chip Debugger Initiated Reset
device exits the Reset state on the system clock rising edge following RESET pin
deassertion. Following a system reset initiated by the external RESET pin, the EXT status
bit in the reset status (RSTSTAT) register is set to 1.
During system reset or when enabled by the GPIO logic, the RESET pin functions as an
open-drain (active low) RESET mode indicator in addition to the input functionality. This
reset output feature allows an Z8 Encore! F083A Series device to reset other components
to which it is connected, even if that reset is caused by internal sources such as POR,
VBO, or WDT events. See
After an internal Reset event occurs, the internal circuitry begins driving the RESET pin
low. The RESET pin is held low by the internal circuitry until the appropriate delay listed
in
A POR is initiated using the On-Chip Debugger by setting the RST bit in the OCD control
register. The On-Chip Debugger block is not reset, but the rest of the chip goes through a
normal system reset. The RST bit automatically clears during the system reset. Following
the system reset, the POR bit in the reset status (RSTSTAT) register is set.
The device enters the STOP mode when the STOP instruction is executed by the eZ8
CPU. For more details on STOP mode, see
Mode Recovery, the CPU is held in reset for about 66 IPO cycles if the crystal oscillator is
disabled or about 5000 cycles if it is enabled.
Stop Mode Recovery does not affect the on-chip registers other than the reset status
(RSTSTAT) register and the oscillator control register (OSCCTL). After any Stop Mode
Recovery, the IPO is enabled and selected as the system clock. If another system clock
source is required or IPO disabling is required, the Stop Mode Recovery code must
reconfigure the oscillator control block such that the correct system clock source is
enabled and selected.
The eZ8 CPU fetches the reset vector at program memory addresses
and loads that value into the program counter. Program execution begins at the reset vector
address. Following Stop Mode Recovery, the STOP bit in the reset status (RSTSTAT)
register is set to 1.
The following sections provide more detailed information about each of the Stop Mode
Recovery sources.
Table 8
on page 23 has elapsed.
Table 10
Port A–D Control Registers
lists the Stop Mode Recovery sources and resulting actions.
Low-Power Modes
on page 44.
Z8 Encore!
Reset and Stop Mode Recovery
on page 33. During Stop
Product Specification
0002H
®
F083A Series
and
0003H
28