Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 76

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

Table 45. Shared Interrupt Select Register (IRQSS)
Table 46. Interrupt Control Register (IRQCTL)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
Interrupt Control Register
Reserved
IRQE
R/W
R/W
7
0
7
0
Because these shared interrupts are edge-triggered, it is possible to generate an interrupt
just by switching from one shared source to another. For this reason, an interrupt must be
disabled before switching between sources.
PA6CS—PA6/Comparator selection
0 = PA6 is used for the interrupt caused by PA6CS interrupt request.
1 = The comparator is used for the interrupt caused by PA6CS interrupt request.
Reserved—Must be 0.
The interrupt control (IRQCTL) register contains the master enable bit for all interrupts.
See
IRQE—Interrupt request enable
This bit is set to 1 by executing an EI (enable interrupts) or IRET (interrupt return)
instruction, or by a direct register write of 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request, reset or by a direct register
write of a 0 to this bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved—Must be 0.
Table
PA6CS
R/W
46.
R
6
0
6
0
R/W
R
5
0
5
0
R/W
R
4
0
4
0
FCEH
FCFH
Reserved
R/W
R
3
0
3
0
Reserved
R/W
Z8 Encore!
R
2
0
2
0
Product Specification
R/W
R
1
0
1
0
®
Interrupt Controller
F083A Series
R/W
R
0
0
0
0
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