Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 90

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

PS026308-1207
Reading the Timer Count Values
Timer Pin Signal Operation
The steps for configuring a timer for CAPTURE/COMPARE mode and for initiating the
count are as follows:
1. Write to the timer control register to:
2. Write to the timer high and low byte registers to set the starting count value (typically
3. Write to the timer reload high and low byte registers to set the compare value.
4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the timer control register to enable the timer.
7. Counting begins on the first appropriate transition of the timer input signal. No
In CAPTURE/COMPARE mode, the elapsed time from timer start to Capture event is
calculated using the following equation:
The current count value in the timers are read while counting (enabled). This capability
has no effect on Timer operation. When the timer is enabled and the timer high byte
register is read, the contents of the timer low byte register are placed in a holding register.
A subsequent read from the timer low byte register returns the value in the holding
register. This operation allows accurate reads of the full 16-bit timer count value when
enabled. When the timers are not enabled, a read from the timer low byte register returns
the actual value in the counter.
Timer output is a GPIO port pin alternate function. The timer output is toggled every time
the counter is reloaded.
–
–
–
–
0001H
interrupt registers.By default, the timer interrupt are generated for both input Capture
and Reload events. You configure the timer interrupt to be generated only at the input
Capture event or the Reload event by setting TICONFIG bit of the TxCTL1 register.
interrupt is generated by the first edge.
Capture Elapsed Time (s)
Disable the timer
Configure the timer for CAPTURE/COMPARE mode
Set the prescale value
Set the capture edge (rising or falling) for the timer input
).
=
(
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Capture Value Start Value
System Clock Frequency (Hz)
–
Z8 Encore!
)
×
Prescale
Product Specification
®
F083A Series
Timers
78