MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 80
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (2Mb)
PCI Express
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the
TX UI.
17.5.1
The AC timing and voltage parameters must be verified at the measurement point, as specified within
0.2 inches of the package pins, into a test/measurement load shown in
80
Compliance Test and Measurement Load
Figure 57. Minimum Receiver Eye Timing and Voltage Compliance Specification
The reference impedance for return loss measurements is 50 Ω to ground for
both the D+ and D– line (that is, as measured by a vector network analyzer
with 50-Ω probes, see
optional for the return loss measurement.
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary.
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
(D+ D– Crossing Point)
V
RX-DIFF
D+ Package
D+ Package
D– Package
= 0 mV
Figure 58. Compliance Test/Measurement Load
+ Package
Silicon
Pin
Pin
Pin
TX
Figure
V
RX-DIFFp-p-MIN
0.4 UI = T
57). Note that the series capacitors, CTX, are
C = C
C = C
NOTE
NOTE
R = 50 Ω
RX-EYE-MIN
TX
TX
> 175 mV
(D+ D– Crossing Point)
R = 50 Ω
V
Figure
RX-DIFF
58.
= 0 mV
Freescale Semiconductor
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