MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 48

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Local Bus
Figure 27
48
Local bus clock to output high impedance for LAD/LDP
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
6. t
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one (1). Also, t
the output (O) going invalid (X) or output hold time.
bypass mode to 0.4 × BV
through the component pin is less than or equal to the leakage current specification.
programmed with the LBCR[AHD] parameter.
complementary signals at BV
LBOTOT
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
provides the AC test load for the local bus.
(first two letters of functional block)(reference)(state)(signal)(state)
Table 47. Local Bus General Timing Parameters (BV
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
LBKHOX
Parameter
DD
Output
symbolizes local bus timing (LB) for the t
of the signal in question for 1.8-V signaling levels.
DD
/2.
DD
/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
Figure 27. Local Bus AC Test Load
Z
0
= 50 Ω
Symbol
t
LBKHOZ2
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
1
LBK
LBK
clock reference (K) to go high (H), with respect to
R
clock reference (K) goes high (H), in this case for
L
DD
= 50 Ω
Min
= 1.8 V DC) (continued)
—
BV
DD
LBIXKH1
Max
2.6
/2
Freescale Semiconductor
symbolizes local bus
LBOTOT
Unit
ns
is
Notes
for
5