MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 45

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2
Table 45
information about the frequency range of local bus see
Freescale Semiconductor
High-level output voltage
(BV
Low-level output voltage
(BV
Local bus cycle time
Local bus duty cycle
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output transition
(LATCH setup and hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and
LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
DD
DD
= min, I
= min, I
describes the general timing parameters of the local bus interface at BV
Local Bus AC Electrical Specifications
OH
OL
= 2 mA)
Table 45. Local Bus General Timing Parameters (BV
= –2 mA)
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Table 44. Local Bus DC Electrical Characteristics (1.8 V DC) (continued)
Parameter
Parameter
Symbol
t
V
V
Symbol
t
t
t
t
t
t
t
LBKH/
t
LBKSKEW
t
t
t
t
t
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
LBKHOX2
LBKHOZ1
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
OH
OL
LBOTOT
t
Section 19.1, “Clock Ranges.”
LBK
t
LBK
1
1.35
Min
—
DD
1.85
Min
7.5
2.5
1.0
1.0
1.5
0.7
0.7
43
—
—
—
—
—
—
= 3.3 V)
—PLL Enabled
Max
0.45
Max
—
150
2.9
2.8
2.7
2.7
2.5
12
57
—
—
—
—
—
—
—
DD
= 3.3 V. For
Unit
Unit
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
V
V
Local Bus
Notes
Notes
7, 8
3, 4
3, 4
3, 4
3, 4
—
—
—
—
—
2
6
3
3
3
3
5
45