MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 49
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 49 of 117
- Download datasheet (2Mb)
Figure 28
Table 48
disabled.
Freescale Semiconductor
Local bus cycle time
Local bus duty cycle
Internal launch/capture clock to LCLK delay
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output transition
(LATCH hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
describes the general timing parameters of the local bus interface at V
through
Output (Address) Signal:
LSDCAS/LSDDQM[0:3]
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Figure 33
Output Signals:
Parameter
Input Signals:
Table 48. Local Bus General Timing Parameters—PLL Bypassed
Input Signal:
LSYNC_IN
LUPWAIT
LAD[0:31]
LGTA
LALE
show the local bus signals.
Figure 28. Local Bus Signals (PLL Enabled)
t
t
LBKHOV1
LBKHOV2
t
LBKHOV3
t
LBKHOV4
t
t
t
t
t
LBIVKH1
LBIVKH2
LBKHOX1
LBKHOX2
LBKHOX2
t
Symbol
LBKH/
t
t
t
t
t
t
t
LBKLOV1
LBIVKH1
LBIXKH1
LBIVKL2
LBIXKL2
LBKHKT
LBOTOT
t
t
t
t
LBK
LBKHOZ1
LBKHOZ2
LBKHOZ2
t
LBK
t
LBOTOT
1
Min
6.75
–0.2
–0.2
1.5
12
43
1.2
7.4
—
t
t
LBIXKH1
LBIXKH2
DD
Max
57
4.9
1.6
—
—
—
—
—
—
= 3.3 V DC with PLL
Unit
ns
ns
ns
ns
ns
ns
ns
ns
%
Local Bus
Notes
4, 5
4, 5
4, 5
4, 5
—
—
—
2
6
49
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