MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 105
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 105 of 117
- Download datasheet (2Mb)
where:
The ratio of I
Solving for T, the equation becomes:
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8544E.
21.1
This device includes six PLLs:
Freescale Semiconductor
•
•
•
•
•
I
I
V
V
V
V
I
I
q = Charge of electron (1.6 × 10
n = Ideality factor (normally 1.0)
K = Boltzman’s constant (1.38 × 10
T = Temperature (Kelvins)
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in
The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e500 core clock and the platform clock is selected using the e500 PLL ratio
configuration bits as described in
The PCI PLL generates the clocking for the PCI bus.
The local bus PLL generates the clock for the local bus.
There are two PLLs for the SerDes block.
fw
s
H
L
d
f
H
L
System Clocking
= Smaller diode bias current
= Saturation current
= Larger diode bias current
= Voltage forward biased
= Voltage at diode
= Forward current
= Diode voltage while I
= Diode voltage while I
H
V
to I
nT =
H
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
– V
L
is usually selected to be 10:1. The above simplifies to the following:
1.986 × 10
L
V
= 1.986 × 10
H
– V
L
–4
L
H
is flowing
–4
is flowing
× nT
–19
Section 19.2, “CCB/SYSCLK PLL Ratio.”
Section 19.3, “e500 Core PLL Ratio.”
–23
C)
Joules/K)
System Design Information
105
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