MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 43
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MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
At recommended operating conditions with OV
Figure 26
Freescale Semiconductor
MDC fall time
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of
3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods ±3 ns. For
4. t
inputs and t
data timing (MD) for the time t
Also, t
(V) relative to the t
convention is used with the appropriate letter: R (rise) or F (fall).
the MgmtClk Clock EC_MDC).
example, with a platform clock of 333 MHz, the min/max delay is 48 ns ± 3 ns. Similarly, if the platform clock is 400 MHz, the
min/max delay is 40 ns ± 3 ns).
plb_clk
Parameter/Condition
MDDVKH
is the platform (CCB) clock.
shows the MII management AC timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(Output)
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
MDC
(Input)
MDIO
MDIO
MDC
Table 41. MII Management AC Timing Specifications (continued)
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
Figure 26. MII Management Interface Timing Diagram
MDC
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
t
MDCH
DD
Symbol
t
MDDVKH
is 3.3 V ± 5%.
t
MDHF
t
MDC
t
MDKHDX
1
Min
—
t
MDCF
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
Ethernet Management Interface Electrical Characteristics
t
MDDXKH
t
Typ
MDCR
—
MDKHDX
Max
10
symbolizes management
Unit
ns
Notes
—
for
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