DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 87

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 1: Device Datasheet for Arria II Devices
Glossary
Table 1–67. Glossary (Part 2 of 4)
December 2010 Altera Corporation
Letter
M,
G,
H,
K,
N,
O,
Q,
L,
I,
R
J
P
J
JTAG Timing
Specifications
PLL
Specifications
R
L
Subject
High-speed I/O block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
PLL Specification parameters:
Diagram of PLL Specifications (1)
Note:
(1) CoreClock can only be fed by dedicated clock input pins or PLL outputs.
Receiver differential input discrete resistor (external to the Arria II device).
TMS
TDO
TCK
TDI
Core Clock
Key
CLK
Reconfigurable in User Mode
t
JCH
t
JPZX
t
JCP
t
JCL
Switchover
f
IN
External Feedback
N
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
f
INPFD
t
Definitions
JPCO
PFD
t
JPSU
M
CP
LF
VCO
K
t
JPH
f
VCO
Counters
t
C0..C9
JPXZ
CLKOUT Pins
f
OUT_EXT
f
OUT
GCLK
RCLK
1–79