DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 37

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 2 of 6)
December 2010 Altera Corporation
fixedclk clock frequency
reconfig_clk clock
frequency
Delta time between
reconfig_clks
Transceiver block minimum
power-down
(gxb_powerdown) pulse
width
Receiver
Supported I/O Standards
Data rate
Absolute V
pin
Operational V
receiver pin
Absolute V
pin
Maximum peak-to-peak
differential input voltage V
(diff p-p) before device
configuration
Maximum peak-to-peak
differential input voltage V
(diff p-p) after device
configuration
Minimum differential eye
opening at receiver serial
input pins
V
Receiver DC Coupling
Support
ICM
(2)
Description
Symbol/
MAX
MIN
(14)
MAX
for a receiver
for a receiver
for a
(13)
ID
ID
V
Data Rate > 5 Gbps
V
ICM
ICM
clock frequency
Equalization = 0
Equalization = 0
reconfiguration
DC gain = 0 dB
DC gain = 0 dB
PCIe Receiver
V
V
600 Mbps to
Conditions
Data Rate =
ICM
ICM
= 1.1 V setting
=1.1 V setting
Dynamic
5 Gbps
setting
setting
Detect
= 0.82 V
= 0.82 V
—
—
—
—
—
—
—
—
(3)
(3)
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
For more information about receiver DC coupling support, refer to the
“DC-Coupled Links” section in the
Devices
37.5
Min
2.5/
-0.4
600
100
165
—
—
—
—
—
—
—
(2)
1
–C3 and –I3
chapter.
1100 ± 10%
820 ± 10%
125
Typ
—
—
—
—
—
—
—
—
—
—
—
—
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
(1)
6375
Max
1.6
1.5
1.6
2.7
1.6
—
50
—
—
—
—
2
37.5
Min
2.5/
-0.4
600
165
165
—
—
—
—
—
—
—
Transceiver Architecture for Arria II
(2)
1
–C4 and –I4
1100 ± 10%
820 ± 10%
Typ
125
—
—
—
—
—
—
—
—
—
—
—
—
3750
Max
1.6
1.5
1.6
2.7
1.6
—
50
—
—
—
—
2
Mbps
MHz
MHz
Unit
ms
mV
mV
mV
mV
µs
V
V
V
V
V
V
1–29