DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 60

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

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Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
PCIe Receiver Jitter Tolerance
Total jitter at 2.5 Gbps
(Gen1)
Total jitter at 5 Gbps (Gen2)
PCIe (Gen 1) Electrical Idle Detect Threshold
V
Serial RapidIO Transmit Jitter Generation
Deterministic jitter
(peak-to-peak)
Total jitter (peak-to-peak)
RX-IDLE-DETDIFFp-p
Description
Symbol/
(8)
(5)
Data rate = 1.25, 2.5,
Data rate = 1.25, 2.5,
Compliance pattern
Compliance pattern
Compliance pattern
Pattern = CJPAT
Pattern = CJPAT
3.125 Gbps
3.125 Gbps
Conditions
(6)
Min
65
—
—
–C3 and –I3
Compliant
Typ
> 0.6
—
—
—
(Note
Max
0.17
0.35
175
Chapter 1: Device Datasheet for Arria II Devices
1),
(2)
Min
65
—
—
(Part 3 of 8)
December 2010 Altera Corporation
–C4 and –I4
Compliant
Typ
—
—
—
—
Switching Characteristics
0.17
0.35
Max
175
Unit
UI
UI
UI
UI
UI